MC9S08JM32CGT Freescale Semiconductor, MC9S08JM32CGT Datasheet - Page 307
![IC MCU 8BIT 32K FLASH 48-QFN](/photos/12/35/123566/mc9s08jm32cgt_sml.jpg)
MC9S08JM32CGT
Manufacturer Part Number
MC9S08JM32CGT
Description
IC MCU 8BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08JM32CLD.pdf
(388 pages)
Specifications of MC9S08JM32CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
37
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
2KB
Cpu Speed
48MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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17.3.9
The STAT reports the transaction status within the USB module. When the MCU receives a TOKDNE
interrupt, the STAT is read to determine the status of the previous endpoint communication. The data in
the status register is valid only when the TOKDNEF interrupt flag is asserted. The STAT register is actually
a read window into a status FIFO maintained by the USB module. When the USB module uses a BD, it
updates the status register. If another USB transaction is performed before the TOKDNE interrupt is
serviced, the USB module will store the status of the next transaction in the STAT FIFO. Thus, the STAT
register is actually a four byte FIFO which allows the microcontroller to process one transaction while the
serial interface engine (SIE) is processing the next. Clearing the TOKDNEF bit in the INTSTAT register
causes the SIE to update the STAT register with the contents of the next STAT value. If the next data in the
STAT FIFO holding register is valid, the SIE will immediately reassert the TOKDNE interrupt.
Freescale Semiconductor
ENDP[3:0]
PIDERR
Reset
CRC5
Field
Field
7–4
1
0
W
R
Status Register (STAT)
CRC5 Interrupt Enable — Setting this bit will enable CRC5 interrupts.
0 Interrupt disabled
1 Interrupt enabled
PIDERR Interrupt Enable — Setting this bit will enable PIDERR interrupts.
0 Interrupt disabled
1 Interrupt enabled
Endpoint Number — These four bits encode the endpoint address that received or transmitted the previous
token. This allows the microcontroller to determine which BDT entry was updated by the last USB transaction.
0000 Endpoint 0
0001 Endpoint 1
0010 Endpoint 2
0011 Endpoint 3
0100 Endpoint 4
0101 Endpoint 5
0110 Endpoint 6
0
7
= Unimplemented or Reserved
0
6
Table 17-12. ERRSTAT Field Descriptions (continued)
ENDP[3:0]
Table 17-13. STAT Field Descriptions
Figure 17-12. Status Register (STAT)
MC9S08JM60 Series Data Sheet, Rev. 3
0
5
0
4
Description
Description
IN
3
0
Universal Serial Bus Device Controller (S08USBV1)
ODD
0
2
0
0
1
0
0
0
307
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