MC9S08JM32CGT Freescale Semiconductor, MC9S08JM32CGT Datasheet - Page 92
![IC MCU 8BIT 32K FLASH 48-QFN](/photos/12/35/123566/mc9s08jm32cgt_sml.jpg)
MC9S08JM32CGT
Manufacturer Part Number
MC9S08JM32CGT
Description
IC MCU 8BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08JM32CLD.pdf
(388 pages)
Specifications of MC9S08JM32CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
37
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
2KB
Cpu Speed
48MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Chapter 6 Parallel Input/Output
6.5.9
Port E parallel I/O function is controlled by the registers listed below.
6.5.10
In addition to the I/O control, port E pins are controlled by the registers listed below.
92
PTEDD[7:0]
PTED[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTEDD7
PTED7
Port E I/O Registers (PTED and PTEDD)
Port E Pin Control Registers (PTEPE, PTESE, PTEDS)
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
0
0
7
7
PTEDD6
PTED6
0
0
6
6
Table 6-22. PTEDD Register Field Descriptions
Figure 6-23. Data Direction for Port E (PTEDD)
Table 6-21. PTED Register Field Descriptions
Figure 6-22. Port E Data Register (PTED)
PTEDD5
MC9S08JM60 Series Data Sheet, Rev. 3
PTED5
0
0
5
5
PTEDD4
PTED4
0
0
4
4
Description
Description
PTEDD3
PTED3
3
0
3
0
PTEDD2
PTED2
0
0
2
2
PTEDD1
Freescale Semiconductor
PTED1
0
0
1
1
PTEDD0
PTED0
0
0
0
0
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