MC9S08RD32CDWE Freescale Semiconductor, MC9S08RD32CDWE Datasheet - Page 112

• Manufacturer Part Number: MC9S08RD32CDWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CDWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Carrier Modulator Transmitter (CMT) Block Description
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As
the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts
required to generate the desired carrier period.
8.5.2
The modulator has three main modes of operation:
The modulator includes a 17-bit down counter with underflow detection. The counter is loaded from the
16-bit modulation mark period buffer registers, CMTCMD1 and CMTCMD2. The most significant bit is
loaded with a logic zero and serves as a sign bit. When the counter holds a positive value, the modulator
gate is open and the carrier signal is driven to the transmitter block.
When the counter underflows, the modulator gate is closed and a 16-bit comparator is enabled that
compares the logical complement of the value of the down-counter with the contents of the modulation
space period register (which has been loaded from the registers CMTCMD3 and CMTCMD4).
When a match is obtained the cycle repeats by opening the modulator gate, reloading the counter with the
contents of CMTCMD1 and CMTCMD2, and reloading the modulation space period register with the
contents of CMTCMD3 and CMTCMD4.
If the contents of the modulation space period register are all zeroes, the match will be immediate and no
space period will be generated (for instance, for FSK protocols that require successive bursts of different
frequencies).
The MCGEN bit in the CMTMSC register must be set to enable the modulator timer.
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Gate the carrier onto the modulator output (time mode)
Control the logic level of the modulator output (baseband mode)
Count carrier periods and instruct the carrier generator to alternate between two carrier frequencies
whenever a modulation period (mark + space counts) expires (FSK mode)
Modulator
Duty Cycle
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
=
---------------------------------------------------------------------
Highcount
Highcount
+
Lowcount
Freescale Semiconductor
Eqn. 8-4