MC9S08RD32CDWE Freescale Semiconductor, MC9S08RD32CDWE Datasheet - Page 164

• Manufacturer Part Number: MC9S08RD32CDWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CDWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Interface (SPI) Module
13.1
Features of the SPI module include:
13.2
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
13.2.1
Figure 13-2
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI1 pin) to
the slave while simultaneously shifting data in (on the MISO1 pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK1 signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS1 pin). In this system, the master device has configured its SS1 pin as an optional
slave select output.
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Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate
Double-buffered transmit and receive
Serial clock phase and polarity options
Slave select output
Selectable MSB-first or LSB-first shifting
7
Features
Block Diagrams
6
SPI System Block Diagram
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
5
GENERATOR
SPI SHIFTER
MASTER
CLOCK
4
3
2
1
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MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Figure 13-2. SPI System Connections
MOSI1
MISO1
SPSCK1
SS1
SPSCK1
MOSI1
MISO1
SS1
7
SLAVE
6
5
SPI SHIFTER
4
3
2
1
Freescale Semiconductor
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