MC9S08RD32CDWE Freescale Semiconductor, MC9S08RD32CDWE Datasheet - Page 78

• Manufacturer Part Number: MC9S08RD32CDWE
• Description: IC MCU 32K FLASH 2K RAM 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CDWE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Parallel Input/Output
6.6.1
Port A pins used as general-purpose I/O pins are controlled by the port A data (PTAD), data direction
(PTADD), and pullup enable (PTAPE) registers.
78
PTAPE[7:0]
PTAD[7:0]
Field
Field
7:0
7:0
Reset
Reset
W
W
R
R
Port A Registers (PTAD, PTAPE, and PTADD)
Port A Data Register Bits — For port A pins that are inputs, reads of this register return the logic level on the
pin. For port A pins that are configured as outputs, reads of this register return the last value written to this
register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled provided the corresponding PTADDn is a logic 0. For port A pins that are
configured as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7
through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup
enable bits enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
PTAPE7
PTAD7
0
0
7
7
PTAPE6
PTAD6
6
0
6
0
Figure 6-7. Pullup Enable for Port A (PTAPE)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Figure 6-6. Port A Data Register (PTAD)
Table 6-2. PTAPE Field Descriptions
Table 6-1. PTAD Field Descriptions
PTAPE5
PTAD5
0
0
5
5
PTAPE4
PTAD4
4
0
4
0
Description
Description
PTAPE3
PTAD3
0
0
3
3
PTAPE2
PTAD2
2
0
2
0
Freescale Semiconductor
PTAPE1
PTAD1
0
0
1
1
PTAPE0
PTAD0
0
0
0
0