R5F21294SNSP#U0 Renesas Electronics America, R5F21294SNSP#U0 Datasheet - Page 277

MCU 3/5V 16K+2K 20PIN-SSOP

R5F21294SNSP#U0

Manufacturer Part Number
R5F21294SNSP#U0
Description
MCU 3/5V 16K+2K 20PIN-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/29r
Datasheet

Specifications of R5F21294SNSP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21294SNSP#U0R5F21294SNSP#UO
Manufacturer:
RENESAS
Quantity:
15 449
R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
Figure 16.8
SS Transmit Data Register
SS Receive Data Register
b7 b6 b5
b7 b6 b5 b4
NOTE:
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Sep 26, 2008
b4
b3
b3 b2 b1 b0
b2
Registers SSTDR and SSRDR
b1
b0
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from
the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
Store the receive data.
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
Symbol
SSTDR
Symbol
SSRDR
Page 258 of 441
(1)
Address
Address
00BEh
00BFh
Function
Function
16. Clock Synchronous Serial Interface
After Reset
After Reset
FFh
FFh
RW
RW
RW
RO

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