R5F21275SNFP#U0 Renesas Electronics America, R5F21275SNFP#U0 Datasheet - Page 291
R5F21275SNFP#U0
Manufacturer Part Number
R5F21275SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21275SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21275SNFP#U0R5F21275SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21275SNFP#U0R5F21275SNFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.11
16.2.2
• SSUMS = 0
• SSUMS = 1 (4-wire bus communication mode),
16.2.2.1
(clock synchronous communication mode)
BIDE = 0 (standard mode), and MSS = 0 (operates
as slave device)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 16.11 shows the Association between Data I/O Pins and SSTRSR Register.
SSTRSR register
SSTRSR register
Sep 26, 2008
SS Shift Register (SSTRSR)
Association between Data I/O Pins and SS Shift Register
Association between Data I/O Pins and SSTRSR Register
Page 272 of 453
SSO
SSI
SSO
SSI
• SSUMS = 1 (4-wire bus communication mode),
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
BIDE = 1 (bidirectional mode)
SSTRSR register
SSTRSR register
16. Clock Synchronous Serial Interface
SSO
SSI
SSO
SSI
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