MC908AP32ACFBE Freescale Semiconductor, MC908AP32ACFBE Datasheet - Page 249

• Manufacturer Part Number: MC908AP32ACFBE
• Description: IC MCU 32K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32ACFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.6 Result Justification
The conversion result may be formatted in four different ways.
All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock control
register (ADICLK).
Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register
high (ADRH). This may be useful if the result is to be treated as an 8-bit result where the least significant
two bits, located in the ADC data register low (ADRL) can be ignored. However, you must read ADRL
after ADRH or else the interlocking will prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC data register high (ADRH) and
the eight LSB bits in ADC data register low (ADRL). This mode of operation typically is used when a 10-bit
unsigned result is desired.
Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit
result, AD9 located in ADRH is complemented. This mode of operation is useful when a result,
represented as a signed magnitude from mid-scale, is needed.
Finally, 8-bit truncation mode will place the eight MSBs in ADC data register low (ADRL). The two LSBs
are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No
interlocking between ADRH and ADRL is present.
15.3.7 Data Register Interlocking
Reading ADRH in any 10-bit mode latches the contents of ADRL until ADRL is read. Until ADRL is read
all subsequent ADC results will be lost. This register interlocking can also be reset by a write to the ADC
status and control register, or ADC clock control register. A power-on reset or reset will also clear the
interlocking. Note that an external conversion request will not reset the lock.
15.3.8 Monotonicity
The conversion process is monotonic and has no missing codes.
15.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion or after an auto-scan conversion cycle. A CPU interrupt is generated if the COCO bit is at
logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. The
interrupt vector is defined in
15.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
Freescale Semiconductor
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Left justified
Right justified
Left justified sign data mode
8-bit truncation
Table 2-1 . Vector
MC68HC908AP A-Family Data Sheet, Rev. 3
Addresses.
Interrupts
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