MC908AP32ACFBE Freescale Semiconductor, MC908AP32ACFBE Datasheet - Page 292

• Manufacturer Part Number: MC908AP32ACFBE
• Description: IC MCU 32K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32ACFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Break Module (BRK)
BRKE — Break Enable Bit
BRKA — Break Active Bit
21.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
21.5.3 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait
mode. This register is used only in emulation mode.
292
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
1 = (When read) Break address match
0 = (When read) No break address match
Note: Writing a logic 0 clears SBSW.
Address:
Address:
Address:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
$FE0C
$FE0D
$FE00
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
Figure 21-6. SIM Break Status Register (SBSR)
R
0
0
Figure 21-4. Break Address Register High (BRKH)
Figure 21-5. Break Address Register Low (BRKL)
MC68HC908AP A-Family Data Sheet, Rev. 3
14
R
6
0
6
6
0
6
13
R
R
5
0
5
5
0
5
= Reserved
12
R
4
0
4
4
0
4
11
R
3
0
3
3
0
3
10
R
2
0
2
2
0
2
SBSW
Note
1
9
0
1
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
R
0
0