MC908AP32ACFBE Freescale Semiconductor, MC908AP32ACFBE Datasheet - Page 33
![IC MCU 32K FLASH 8MHZ 44-QFP](/photos/39/61/396111/4243290_sml.jpg)
MC908AP32ACFBE
Manufacturer Part Number
MC908AP32ACFBE
Description
IC MCU 32K FLASH 8MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP16ACFBER.pdf
(316 pages)
Specifications of MC908AP32ACFBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
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Part Number:
MC908AP32ACFBE
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Quantity:
44
Company:
Part Number:
MC908AP32ACFBE
Manufacturer:
Freescale Semiconductor
Quantity:
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MC908AP32ACFBE
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† One-time writable register after each reset.
† One-time writable register after each reset.
Freescale Semiconductor
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
Addr.
IRQ2 Status and Control Reg-
IRQ1 Status and Control Reg-
Timer 1 Counter Modulo Reg-
Timer 1 Channel 0 Status and
Keyboard Status and Control
Control Register (T1SC0)
Configuration Register 2
Configuration Register 1
Timer 1 Counter Modulo
Register Name
Timer 1 Status and
Keyboard Interrupt
Control Register
Timer 1 Counter
Timer 1 Counter
Enable Register
U = Unaffected
Register High
Register Low
Register Low
(CONFIG2)
(CONFIG1)
(INTSCR2)
(INTSCR1)
(T1MODH)
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
(T1MODL)
(T1CNTH)
(T1CNTL)
ister High
(KBSCR)
Register
(KBIER)
(T1SC)
ister
ister
†
†
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
MC68HC908AP A-Family Data Sheet, Rev. 3
X = Indeterminate
ICLKDIS
COPRS
STOP_
KBIE7
Bit 15
Bit 15
CH0F
Bit 7
TOF
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
PUC0ENB
LVISTOP
RCLKEN
STOP_
CH0IE
KBIE6
TOIE
14
14
6
0
0
0
0
0
0
0
0
0
0
6
0
1
6
1
0
LVIRSTD
XCLKEN
TSTOP
STOP_
KBIE5
MS0B
13
13
5
0
0
0
0
0
0
0
0
0
1
0
5
0
1
5
1
0
= Unimplemented
OSCCLK1 OSCCLK0
LVIPWRD
KBIE4
MS0A
TRST
12
12
4
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
4
1
0
LVIREGD
ELS0B
KBIE3
IRQ2F
IRQ1F
KEYF
11
11
3
0
0
0
0
0
0
0
0
0
3
0
1
3
1
0
SSREC
ELS0A
KBIE2
ACK2
ACK1
ACK
PS2
10
10
R
2
0
0
0
0
0
0
0
0
0
0
0
0
2
0
1
2
1
0
= Reserved
IMASK2
IMASK1
IMASK
KBIE1
STOP
TOV0
PS1
1
0
0
0
0
0
0
0
0
9
0
1
0
9
1
1
1
0
Monitor ROM
SCIBDSRC
CH0MAX
MODE2
MODE1
MODE
KBIE0
COPD
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PS0
0
0
0
0
0
0
0
0
0
1
1
0
33
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