MC908GR32ACFAE Freescale Semiconductor, MC908GR32ACFAE Datasheet - Page 173
![IC MCU 32K FLASH 8MHZ 48-LQFP](/photos/12/37/123791/mc908gr32acfae_sml.jpg)
MC908GR32ACFAE
Manufacturer Part Number
MC908GR32ACFAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32ACFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32ACFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC908GR32ACFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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13.8.5 ESCI Status Register 2
ESCI status register 2 (SCS2) contains flags to signal these conditions:
BKF — Break Flag Bit
RPF — Reception in Progress Flag Bit
13.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
Freescale Semiconductor
•
•
This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin. In SCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after 1s again appear on the RxD pin
followed by another break character. Reset clears the BKF bit.
This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search.
RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling
RPF before disabling the ESCI module or entering stop mode can show whether a reception is in
progress.
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register.
1 = Break character detected
0 = No break character detected
1 = Reception in progress
0 = No reception in progress
Break character detected
Incoming data
Address:
Address:
Do not use read-modify-write instructions on the ESCI data register.
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$0017
$0018
Bit 7
Bit 7
R7
T7
0
0
Figure 13-15. ESCI Status Register 2 (SCS2)
= Unimplemented
Figure 13-16. ESCI Data Register (SCDR)
R6
T6
6
0
0
6
R5
T5
5
0
0
5
NOTE
Unaffected by reset
R4
T4
4
0
0
4
R3
T3
3
0
0
3
R2
T2
2
0
0
2
BKF
R1
T1
1
0
1
Bit 0
RPF
Bit 0
R0
T0
0
I/O Registers
173
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