MC908GR32ACFAE Freescale Semiconductor, MC908GR32ACFAE Datasheet - Page 51
![IC MCU 32K FLASH 8MHZ 48-LQFP](/photos/12/37/123791/mc908gr32acfae_sml.jpg)
MC908GR32ACFAE
Manufacturer Part Number
MC908GR32ACFAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32ACFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32ACFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC908GR32ACFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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HVEN — High-Voltage Enable Bit
MASS — Mass Erase Control Bit
ERASE — Erase Control Bit
PGM — Program Control Bit
2.7.2.2 FLASH-2 Block Protect Register
The FLASH-2 block protect register (FL2BPR) is implemented as a byte within the FLASH-1 memory;
therefore, can only be written during a FLASH-1 programming sequence. The value in this register
determines the starting location of the protected range within the FLASH-2 memory.
FL2BPR[7:0] — Block Protect Register Bits 7 to 0
Freescale Semiconductor
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
Setting this read/write bit configures the FLASH-2 array for mass or page erase operation.
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be set at the same time.
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
These eight bits represent bits [14:7] of a 16-bit memory address. Bit 15 is a 0 and bits [6:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH-2 memory for block
protection. FLASH-2 is protected from this start address to the end of FLASH-2 memory at $7FFF.
With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries)
within the FLASH-2 array.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1 = Mass erase operation selected
0 = Page erase operation selected
1 = Erase operation selected
0 = Erase operation unselected
1 = Program operation selected
0 = Program operation unselected
Address:
The FLASH-2 block protect register (FL2BPR) controls the block protection
for the FLASH-2 array. However, FL2BPR is implemented within the
FLASH-1 memory array and therefore, the FLASH-1 control register
(FL1CR) must be used to program/erase FL2BPR.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
$FF81
Figure 2-8. FLASH-2 Block Protect Register (FL2BPR)
BPR7
Bit 7
BPR6
6
BPR5
5
NOTE
Unaffected by reset
BPR4
4
BPR3
3
BPR2
2
BPR1
1
FLASH-2 Memory (FLASH-2)
BPR0
Bit 0
51
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