MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 580

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.3.4
CSR3 contains the BDM flash clock divider (BFCDIV) value in a format similar to HCS08 devices.
There are multiple ways to reference CSR3. They are summarized in
26-16
APCDIV16
PSTBRM
PSTBSS
Field
4–3
2–0
6
5
WRITE_CSR3_BYTE Writes CSR3[31
READ_CSR3_BYTE Reads CSR3[31
Method
Automatic PC synchronization divide cycle counts by 16. This bit divides the cycle counts for automatic SYNC_PC
command insertion by 16. See the APCSC and APCENB field descriptions.
Reserved, must be cleared.
PST trace buffer recording mode. Defines the trace buffer recording mode. The start and stop recording conditions
are defined by the PSTBSS field.
00 Non-obstrusive, normal recording mode
01 Obtrusive, normal recording
10 Non-obtrusive, PC profile recording. Automatic PC synchronization must be enabled (see XCSR[APCSC,
11 Obtrusive, PC profile recording. Automatic PC synchronization must be enabled (see XCSR[APCSC,
The terms obtrusive and non-obtrusive are defined as:
PST trace buffer start/stop definition. Specifies the start and stop conditions for PST trace buffer recording. In
certain cases, the start and stop conditions are defined by the breakpoint registers. The remaining breakpoint
registers are available for trigger configurations.
Configuration/Status Register 3 (CSR3)
• Non-obtrusive—The core is not halted. The PST trace buffer is overwritten unless a PSTB start/stop
• Obtrusive—The core is halted when the PSTB trace buffer reaches its full level (full before overwriting). The
combination results in less than or equal to 64 PSTB captures.
PSTB trace buffer contents are available by the BDM PSTB_READ commands. The PSTB trace buffer write
address resets and the CPU resumes upon a BDM GO command.
APCENB], CSR2[APCDIV16], and CSR[BTB]).
APCENB], CSR2[APCDIV16], and CSR[BTB]).
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 26-9. CSR2 Field Descriptions (continued)
PSTBSS
Table 26-10. CSR3 Reference Summary
000
001
010
011
100
101
110
111
–
–
24] from the BDM interface. Available in all modes.
24] from the BDM interface. Available in all modes.
ABxR{& DBR/DBMR}
Start Condition
PBR0/PBMR
Trace buffer disabled, no recording
PBR1
Description
Unconditional recording
Reference Details
ABxR{& DBR/DBMR}
ABxR{& DBR/DBMR}
Stop Condition
PBR0/PBMR
PBR0/PBMR
Table
PBR1
PBR1
26-10.
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