DF2211CUNP24V Renesas Electronics America, DF2211CUNP24V Datasheet
DF2211CUNP24V
Specifications of DF2211CUNP24V
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DF2211CUNP24V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2218 Group, 16 H8S/2212 Group Hardware Manual ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition (only for revised versions) The list of revisions is a ...
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This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology’s original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general ...
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In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, ...
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Main Revisions for This Edition Item Page 1.1 Overview 1 • On-chip memory 2 1.2 Internal Block 3 Diagram Revision (See Manual for Details) Table amended H8S/2218 Group ROM Part No. Flash memory Version HD64F2218 HD64F2218U HD64F2218CU HD64F2217CU Masked ROM ...
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Item Page 1.2 Internal Block 3 Diagram Figure 1.1 Internal Block Diagram of HD64F2218, HD64F2218U, HD64F2218CU and HD642217CU Figure 1.2 Internal 4 Block Diagram of HD6432217 Figure 1.3 Internal 5 Block Diagram of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211, HD64F2211U, HD64F2211CU and ...
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Item Page 1.2 Internal Block 6 Diagram Figure 1.4 Internal Block Diagram of HD6432211, HD6432210 and HD6432210S 1.3 Pin 7 Arrangements Figure 1.5 Pin Arrangements of HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU (TFP- 100G, TFP-100GV) Revision (See Manual for Details) Note ...
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Item Page Figure 1.6 Pin 8 Arrangements of HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU (BP-112, BP-112V) Figure 1.7 Pin 9 Arrangements of HD6432217 (TFP- 100G, TFP-100GV) Figure 1.8 Pin 10 Arrangements of HD6432217 (BP-112, BP-112V) Figure 1.9 Pin 11 Arrangements of ...
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Item Page 1.3 Pin Arrangement 12 Figure 1.10 Pin Arrangements of HD6432211, HD6432210 and HD6432210S (FP- 64E, FP-64EV) Figure 1.11 Pin 13 Arrangements of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211, HD64F2211U, HD64F2211CU and HD64F2210CU (TNP-64B, TNP-64BV) Figure 1.12 Pin 14 Arrangements of ...
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Item Page 3.4 Memory Map in 77 Each Operating Mode Figure 3.1 Memory Map in Each Operating Mode for HD64F2218, HD64F2218U and HD64F2218CU Figure 3.2 Memory 78 Map in Each Operating Mode for HD64F2217CU Figure 3.4 Memory 80 Map in ...
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Item Page 12.3.7 Serial Status 377 to Register (SSR) 379 • Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) • Smart Card Interface 380 to 383 Mode (When SMIF in SCMR is 1) Revision (See Manual for ...
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Item Page 12.3.11 Bit Rate 401 Register (BRR) • Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) 12.4.2. Receive Data 405 Sampling Timing and Reception Margin in Asynchronous Mode Figure 12.6 Receive Data Sampling Timing in Asynchronous ...
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Item Page 13.3.2 IDCODE 454 Register (IDCODE) Table 13.3 IDCODE Register Configuration 14.3.5 USB FIFO 475 to Clear Register 0 476 (UFCLR0) 14.8.16 Clearing the 533 FIFO when DMA Transfer Is Enabled Section 16 RAM 551 Revision (See Manual for ...
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Item Page Section 16 RAM 551 17.1 Features 553 • Size: • Two flash memory operating modes Rev.7.00 Dec. 24, 2008 Page xvi of liv REJ09B0074-0700 Revision (See Manual for Details) Table amended Product Class ROM Type H8S/2218 HD64F2218 Flash ...
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Item Page 17.1 Features 554 Figure 17.1 Block Diagram of Flash Memory 17.3 Block 558 Configuration Figure 17.5 Flash Memory Block Configuration (HD64F2218, HD64F2218U, HD64F2218CU, HD64F2212, HD64F2212U, HD64F2212CU) Figure 17.6 Flash 559 Memory Block Configuration (HD64F2217CU, HD64F2211, HD64F2211U, HD64F2211CU) Figure ...
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Item Page 17.6 On-Board 567 Programming Modes Table 17.3 Setting On-Board Programming Modes 17.6.1 SCI Boot Mode 569 (HD64F2218, HD64F2212, and HD64F2211) 17.6.2 USB Boot 573 Mode (HD64F2218U, HD64F2212U, and HD64F2211U) Rev.7.00 Dec. 24, 2008 Page xviii of liv REJ09B0074-0700 ...
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Item Page 22.2 Power Supply 658 Voltage and Operating Frequency Range Figure 22.1 Power Supply Voltage and Operating Ranges Revision (See Manual for Details) Figure amended (1) Mask ROM versions (except for HD6432210S) Condition A: Frequency f System clock 24 ...
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Item Page B. Product Model 689 to Lineup 690 All trademarks and registered trademarks are the property of their respective owners. Rev.7.00 Dec. 24, 2008 Page xx of liv REJ09B0074-0700 Revision (See Manual for Details) Table amended Product Class Part ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Arrangements.............................................................................................................. 1.4 Pin Functions in Each Operating Mode ............................................................................ 15 1.5 Pin Functions .................................................................................................................... 21 Section 2 CPU ...................................................................................................................... 31 2.1 Features ............................................................................................................................. 31 2.1.1 Differences between H8S/2600 ...
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Processing States ............................................................................................................... 64 2.9 Usage Notes....................................................................................................................... 66 2.9.1 Note on TAS Instruction Usage ........................................................................... 66 2.9.2 STM/LTM Instruction Usage ............................................................................... 66 2.9.3 Note on Bit Manipulation Instructions ................................................................. 66 2.9.4 Accessing Registers Containing Write-Only Bits ................................................ 68 Section ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 96 5.3.4 IRQ Status Register (ISR).................................................................................... 98 5.4 Interrupt Sources ............................................................................................................... 99 5.4.1 External Interrupts ............................................................................................... 99 5.4.2 Internal Interrupts................................................................................................. 100 5.5 Interrupt Exception Handling Vector Table...................................................................... 101 5.6 Interrupt ...
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Valid Strobes ........................................................................................................ 135 6.6.3 Basic Timing ........................................................................................................ 136 6.6.4 Wait Control......................................................................................................... 145 6.7 Burst ROM Interface ......................................................................................................... 147 6.7.1 Basic Timing ........................................................................................................ 147 6.7.2 Wait Control......................................................................................................... 149 6.8 Idle Cycle .......................................................................................................................... 149 6.9 Bus Release ....................................................................................................................... 153 6.9.1 ...
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DMAC Register Access during Operation........................................................... 207 7.6.2 Module Stop......................................................................................................... 208 7.6.3 Medium-Speed Mode........................................................................................... 208 7.6.4 Activation Source Acceptance ............................................................................. 209 7.6.5 Internal Interrupt after End of Transfer................................................................ 209 7.6.6 Channel Re-Setting .............................................................................................. 209 Section 8 I/O Ports .............................................................................................................. 211 ...
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Port B Register (PORTB)..................................................................................... 240 8.7.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 241 8.7.5 Pin Functions........................................................................................................ 242 8.7.6 Port B Input Pull-Up MOS States ........................................................................ 244 8.8 Port C (H8S/2218 Group Only)......................................................................................... 245 8.8.1 Port C Data ...
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Register Descriptions ........................................................................................................ 278 9.3.1 Timer Control Register (TCR) ............................................................................. 279 9.3.2 Timer Mode Register (TMDR) ............................................................................ 282 9.3.3 Timer I/O Control Register (TIOR) ..................................................................... 284 9.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 293 9.3.5 Timer Status Register (TSR)................................................................................ ...
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Notes on Register Access ..................................................................................... 346 10.5.2 Contention between Timer Counter (TCNT) Write and Increment...................... 347 10.5.3 Changing Value of CKS2 to CKS0 ...................................................................... 348 10.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode ................ 348 10.5.5 Internal ...
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Bit Rate Register (BRR) ...................................................................................... 395 12.4 Operation in Asynchronous Mode .................................................................................... 403 12.4.1 Data Transfer Format ........................................................................................... 404 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 405 12.4.3 Clock.................................................................................................................... 406 12.4.4 SCI Initialization (Asynchronous Mode) ...
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Section 13 Boundary Scan Function 13.1 Features ............................................................................................................................. 449 13.2 Pin Configuration .............................................................................................................. 451 13.3 Register Descriptions......................................................................................................... 452 13.3.1 Instruction Register (INSTR) ............................................................................... 452 13.3.2 IDCODE Register (IDCODE).............................................................................. 454 13.3.3 BYPASS Register (BYPASS).............................................................................. 454 13.3.4 Boundary Scan Register (BSCANR).................................................................... 454 ...
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USB Configuration Value Register (UCVR) ....................................................... 488 14.3.27 USB Test Register 0 (UTSTR0) .......................................................................... 489 14.3.28 USB Test Register 1 (UTSTR1) .......................................................................... 490 14.3.29 USB Test Registers 2 and (UTSTR2, UTSTRA to UTSTRF).................. 492 14.3.30 Module ...
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Input/Output Pins .............................................................................................................. 537 15.3 Register Descriptions......................................................................................................... 537 15.3.1 A/D Data Registers (ADDRA to ADDRD).............................................. 538 15.3.2 A/D Control/Status Register (ADCSR)................................................................ 538 15.3.3 A/D Control Register (ADCR)............................................................................. 540 15.4 Interface to Bus Master ..................................................................................................... 541 15.5 ...
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Erase/Erase-Verify............................................................................................... 581 17.9 Program/Erase Protection.................................................................................................. 583 17.9.1 Hardware Protection ............................................................................................ 583 17.9.2 Software Protection.............................................................................................. 583 17.9.3 Error Protection.................................................................................................... 583 17.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 584 17.11 Programmer Mode ............................................................................................................ 585 17.12 Power-Down States for Flash Memory............................................................................. 586 ...
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Sleep Mode........................................................................................................................ 618 20.3.1 Transition to Sleep Mode ..................................................................................... 618 20.3.2 Exiting Sleep Mode .............................................................................................. 618 20.4 Software Standby Mode .................................................................................................... 619 20.4.1 Transition to Software Standby Mode.................................................................. 619 20.4.2 Clearing Software Standby Mode ........................................................................ 619 20.4.3 Setting Oscillation ...
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Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings ............................................................................................. 657 22.2 Power Supply Voltage and Operating Frequency Range .................................................. 658 22.3 DC Characteristics ............................................................................................................ 659 22.4 AC Characteristics ............................................................................................................ 663 22.4.1 Clock Timing ....................................................................................................... 664 22.4.2 Control Signal Timing ......................................................................................... ...
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Rev.7.00 Dec. 24, 2008 Page xxxvi of liv REJ09B0074-0700 ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of HD64F2218, HD64F2218U, HD64F2218CU and HD642217CU......................................................................................................... Figure 1.2 Internal Block Diagram of HD6432217 ................................................................. Figure 1.3 Internal Block Diagram of HD64F2212, HD64F2212U, HD64F2212CU, HD64F2211, HD64F2211U, HD64F2211CU and HD64F2210CU....................... Figure 1.4 Internal Block ...
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Section 3 MCU Operating Modes Figure 3.1 Memory Map in Each Operating Mode for HD64F2218, HD64F2218U and HD64F2218CU....................................................................................................... 77 Figure 3.2 Memory Map in Each Operating Mode for HD64F2217CU .................................. 78 Figure 3.3 Memory Map in Each Operating Mode for ...
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Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) ...... 140 Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)........................... 141 Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (1) (Even ...
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Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.1 Block Diagram of TPU ........................................................................................... 274 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ..................... 299 Figure 9.2 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] ...
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Figure 9.41 TCIU Interrupt Setting Timing............................................................................... 329 Figure 9.42 Timing for Status Flag Clearing by CPU ............................................................... 330 Figure 9.43 Timing for Status Flag Clearing by DMAC Activation ......................................... 330 Figure 9.44 Phase Difference, Overlap, and Pulse Width in Phase ...
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Figure 12.4 Example of Average Transfer Rate Setting when TPU Clock Is Input (4)............ 394 Figure 12.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 403 Figure 12.6 Receive Data Sampling Timing in Asynchronous ...
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Figure 12.35 Clock Halt and Restart Procedure .......................................................................... 437 Figure 12.36 Example of Communication Using the SCI Select Function ................................. 438 Figure 12.37 Example of Communication Using the SCI Select Function ................................. 439 Figure 12.38 Example of Clocked Synchronous Transmission ...
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Figure 14.18 EP1 Bulk-In Transfer Operation............................................................................. 514 Figure 14.19 EP2 Bulk-Out Transfer Operation .......................................................................... 515 Figure 14.20 Forcible Stall by Firmware ..................................................................................... 518 Figure 14.21 Automatic Stall by USB Function Module ............................................................. 519 Figure 14.22 EP1PKTE Operation in UTRG0............................................................................. 521 ...
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Figure 17.13 Program/Program-Verify Flowchart....................................................................... 580 Figure 17.14 Erase/Erase-Verify Flowchart ................................................................................ 582 Figure 17.15 Memory Map in Programmer Mode....................................................................... 585 Figure 17.16 Power-On/Off Timing (Boot Mode)....................................................................... 589 Figure 17.17 Power-On/Off Timing (User Program Mode) ........................................................ 590 Figure 17.18 Mode Transition Timing ...
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Figure 22.7 Basic Bus Timing (Two-State Access) ................................................................... 670 Figure 22.8 Basic Bus Timing (Three-State Access) ................................................................. 671 Figure 22.9 Basic Bus Timing (Three-State Access with One Wait State)................................ 672 Figure 22.10 Burst ROM Access Timing (Two-State Access) .................................................... 673 ...
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Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode for H8S/2218 Group................................ 15 Table 1.2 Pin Functions in Each Operating Mode for H8S/2212 Group................................ 18 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ 46 Table 2.2 Operation Notation ................................................................................................. ...
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Section 6 Bus Controller Table 6.1 Pin Configuration.................................................................................................... 117 Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ........................................ 129 Table 6.3 Data Buses Used and Valid Strobes........................................................................ 135 Table 6.4 Pin States in Idle Cycle........................................................................................... 152 Table 6.5 ...
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Table 8.21 P31 Pin Function .................................................................................................... 226 Table 8.22 P30 Pin Function .................................................................................................... 226 Table 8.23 P74 Pin Function .................................................................................................... 231 Table 8.24 P71 Pin Function .................................................................................................... 231 Table 8.25 P70 Pin Function .................................................................................................... 231 Table 8.26 P77 Pin Function ...
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Table 8.62 PD0 Pin Function.................................................................................................... 253 Table 8.63 Input Pull-Up MOS States (Port D) ........................................................................ 254 Table 8.64 PE7 Pin Function .................................................................................................... 257 Table 8.65 PE6 Pin Function .................................................................................................... 257 Table 8.66 PE5 Pin Function .................................................................................................... 258 Table 8.67 PE4 ...
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Table 9.3 CCLR2 to CCLR0 (channel 0) ............................................................................... 280 Table 9.4 CCLR2 to CCLR0 (channels 1 and 2).................................................................... 280 Table 9.5 TPSC2 to TPSC0 (channel 0)................................................................................. 281 Table 9.6 TPSC2 to TPSC0 (channel 1)................................................................................. 281 Table 9.7 TPSC2 to TPSC0 ...
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Table 12.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)............. 402 Table 12.10 Serial Transfer Formats (Asynchronous Mode)...................................................... 404 Table 12.11 SSR Status Flags and Receive Data Handling ........................................................ 411 Table 12.12 SCI Interrupt Sources ............................................................................................. 440 Table ...
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Table 19.2 Crystal Resonator Characteristics........................................................................... 600 Table 19.3 External Clock Input Conditions ............................................................................ 601 Table 19.4 External Clock Input Conditions when Duty Adjustment Circuit Is not Used....... 602 Section 20 Power-Down Modes Table 20.1 LSI Internal States in Each Mode........................................................................... ...
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Rev.7.00 Dec. 24, 2008 Page liv of liv REJ09B0074-0700 ...
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Overview • High-speed H8S/2000 central processing unit with 16-bit architecture ⎯ Upward-compatible with H8/300 and H8/300H CPUs on an object level ⎯ Sixteen 16-bit general registers ⎯ 65 basic instructions • Various peripheral functions ⎯ DMA controller (DMAC) ⎯ ...
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H8S/2212 Group ROM Flash memory Version Masked ROM Version • General I/O ports I/O pins: 69 for the H8S/2218 Group, 37 for the H8S/2212 Group • Supports various power-down states • Compact package Package Code* TQFP-100 TFP-100G, TFP-100GV P-LFBGA-112 BP-112, ...
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Internal Block Diagram The internal block diagram of the HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU is shown in figure 1.1. The internal block diagram of the HD6432217 is shown in figure 1.2. The internal block diagram of the HD64F2212, HD64F2212U, ...
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MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLVSS OSC1 OSC2 STBY RES NMI FWE* 1 USPND/TMOW USD+ USD- UBPM VBUS PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 Notes: NC (no connection): These pins should not be ...
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MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLVSS OSC1 OSC2 STBY RES NMI FWE USPND/TMOW USD+ USD- UBPM VBUS PF7 / φ PF3 /ADTRG/IRQ3 PF0 /IRQ2 PG1 /IRQ7 Port 1 Note: NC (no connection): This pin should not be connected; it ...
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MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLVSS OSC1 OSC2 STBY RES NMI FWE* 1 USPND/TMOW USD+ USD- UBPM VBUS PF7 / φ PF3 /ADTRG/IRQ3 PF0 /IRQ2 PG1 /IRQ7 Notes: NC (no connection): These pins should not be connected; they should ...
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Pin Arrangements The pin arrangements of the HD64F2218, HD64F2218U, HD64F2218CU and HD64F2217CU are shown in figures 1.5 and 1.6. The pin arrangements of the HD6432217 are shown in figures 1.7 and 1.8. The pin arrangements of the HD64F2212, HD64F2212U, ...
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PD3/D11 PD0/D8 10 PD5/D13 PD4/D12 PD2/D10 9 FWE PD7/D15 TDO EMLE NMI * * 7 TRST TDI TMS 6 PF7/φ VSS VCC PF3/LWR/ 5 ADTRG/ PF5/RD PF4/HWR IRQ3 PF0/ 4 BREQ/ PF2/WAIT ...
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PD4/D12 76 PD5/D13 77 PD6/D14 78 PD7/D15 79 1 FWE* 80 NMI NC* 87 VCC 88 PF7/φ 89 VSS 90 PF6/AS 91 PF5/RD ...
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PD3/D11 PD0/D8 10 PD5/D13 PD4/D12 PD2/D10 *1 9 FWE PD7/D15 NMI * PF7/φ VSS VCC PF3/LWR/ 5 ADTRG/ PF5/RD PF4/HWR IRQ3 PF0/ ...
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FWE 50 NMI 51 EMLE* 52 TDO/P77* 53 TCK/P76* 54 TMS/P75* TRST/NC* 55 TDI/PG0 VCC 58 PF7/φ 59 VSS 60 PF3/ADTRG/IRQ3 ...
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FWE NMI P77 P76 P75 NC* 2 PG0* 56 VCC ...
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FWE 50 NMI 51 EMLE* 52 TDO/P77* TCK/P76 TMS/P75* TRST/NC TDI/PG0* 57 VCC 58 PF7/φ 59 VSS 60 PF3/ADTRG/IRQ3 ...
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FWE NMI P77 P76 P75 NC* 2 PG0* 56 VCC 57 58 PF7/φ 59 VSS 60 PF3/ADTRG/IRQ3 61 PF0/IRQ2 62 PA3/SCK2 63 PA2/RXD2 PA1/TXD2 64 Notes: ...
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Pin Functions in Each Operating Mode Table 1.1 shows the pin functions in each operating mode for the H8S/2218 Group, and table 1.2 shows that for the H8S/2212 Group. Table 1.1 Pin Functions in Each Operating Mode for H8S/2218 ...
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Pin No. TFP-100G, BP-112, TFP-100GV BP-112V Modes PG2/CS2 27 L2 PG3/CS1 28 H4 PG4/CS0 29 K3 VBUS 30 L3 P36 (PUDP DrVCC 32 K4 USD USD DrVSS 35 J5 P97/AN15 ...
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Pin No. TFP-100G, BP-112, TFP-100GV BP-112V Modes H10 P71/CS5 STBY 57 H11 RES VSS 60 G11 XTAL 61 G10 EXTAL 62 F9 VCC 63 F11 P70/CS4 64 F10 PE0/ PE1/D1 66 ...
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Pin No. TFP-100G, BP-112, TFP-100GV BP-112V Modes 4, 5 TRST/ TDI/ VCC 89 A6 PF7/φ VSS HWR PF3/LWR/ADTRG/IRQ3 95 A4 PF2/WAIT 96 ...
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Pin No. FP-64E, FP-64EV, TNP-64B, TNP-64BV Mode 7 10 MD1 11 MD2 12 USPND/TMOW 13 P30/TxD0 14 P31/RxD0 15 P32/SCK0/IRQ4 16 PG1/IRQ7 17 VBUS 18 P36(PD+) 19 DrVCC 20 USD+ 21 USD- 22 DrVSS 23 P97/AN15 24 P96/AN14 25 Vref ...
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Pin No. FP-64E, FP-64EV, TNP-64B, TNP-64BV Mode 7 39 EXTAL 40 VCC 41 PE0 42 PE1 43 PE2 44 PE3 45 PE4 46 PE5 47 PE6 48 PE7 49 FWE 50 NMI 51 EMLE/NC 52 TDO/P77 53 TCK/P76 54 TMS/P75 ...
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Pin Functions TFP-100G, Type Symbol TFP-100GV Power VCC 62 supply 88 VSS 59 90 PLLVCC 48 PLLVSS 46 Clock XTAL 60 EXTAL 61 OSC1 54 OSC2 53 φ 89 Operating MD2 16 mode MD1 15 control MD0 14 Pin ...
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TFP-100G, Type Symbol TFP-100GV RES* System 58 control STBY* 57 MRES 55 BREQ 97 BACK 96 FWE 80 EMLE 82 Interrupts NMI* 81 IRQ7 25 IRQ4 24 IRQ3 94 IRQ2 97 IRQ1 8 IRQ0 6 Rev.7.00 Dec. 24, 2008 Page ...
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TFP-100G, Type Symbol TFP-100GV Address bus A23 5 A22 4 A21 3 A20 2 A19 98 A18 99 A17 100 A16 1 A15 52 A14 51 A13 50 A12 49 A11 40 A10 ...
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TFP-100G, Type Symbol TFP-100GV Data bus D15 79 D14 78 D13 77 D12 76 D11 75 D10 CS5 Bus ...
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TFP-100G, Type Symbol TFP-100GV HWR Bus control 93 LWR 94 WAIT 95 16-bit timer TCLKA 4 pulse unit TCLKB 5 (TPU) TCLKC 7 TCLKD 9 TIOCA0 2 TIOCB0 3 TIOCC0 4 TIOCD0 5 TIOCA1 6 TIOCB1 7 TIOCA2 8 TIOCB2 ...
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TFP-100G, Type Symbol TFP-100GV Serial TxD2 100 communication TxD0 22 interface (SCI) RxD2 99 RxD0 23 SCK2 98 SCK0 24 A/D converter AN15 35 AN14 36 AN3 42 AN2 43 AN1 44 AN0 45 ADTRG 94 Vref 41 Boundary TMS ...
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TFP-100G, Type Symbol TFP-100GV USB USD+* 32 USD-* 33 VBUS* 29 USPND 21 UBPM 47 P36 30 (PUPD+) I/O port P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P36 30 P32 24 ...
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TFP-100G, Type Symbol TFP-100GV ⎯ I/O port P77 ⎯ P76 ⎯ P75 P74 55 P71 56 P70 63 P97 35 P96 36 PA3 98 PA2 99 PA1 100 PA0 1 PB7 52 PB6 51 PB5 50 PB4 49 PB3 40 ...
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TFP-100G, Type Symbol TFP-100GV I/O port PD7 79 PD6 78 PD5 77 PD4 76 PD3 75 PD2 74 PD1 73 PD0 72 PE7 71 PE6 70 PE5 69 PE4 68 PE3 67 PE2 66 PE1 65 PE0 64 PF7 89 ...
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Rev.7.00 Dec. 24, 2008 Page 30 of 698 REJ09B0074-0700 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and ...
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Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode Note: * Normal mode is not available in this LSI. • Power-down state ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been ...
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CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 ...
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H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) ...
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Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper 16-bit segments of 32-bit ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a ...
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Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and ...
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General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by ...
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Bit Bit Name Initial Value 1 V undefined 0 C undefined 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt ...
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Data Type Register Number 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data Figure 2.9 General Register Data Formats (1) Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn ...
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Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made ...
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Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 5 LDM* , STM* MOVFPE* Arithmetic ADD, SUB, CMP, NEG operations ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* ...
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Table of Instructions Classified by Function Tables 2.3 to 2.10 summarizes the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General register (destination)* Rs ...
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Table 2.3 Data Transfer Instructions 1 Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B ...
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Table 2.4 Arithmetic Operations Instructions 1 Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and data in a ...
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Instruction Size* Function 0 – Rd → Rd NEG B/W/L Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd EXTU W/L Extends the lower 8 bits of a 16-bit register to ...
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Table 2.6 Shift Instructions Instruction Size* Function Rd (shift) → Rd SHAL B/W/L SHAR Performs an arithmetic shift on general register contents. 1-bit or 2 bit shift is possible. Rd (shift) → Rd SHLL B/W/L SHLR Performs an logical shift ...
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Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower ...
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Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ∼ (<bit-No.> of ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2.9 System Control Instruction Instruction Size* Function TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC B/W Moves the ...
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Table 2.10 Block Data Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B – else next ≠ 0 then EEPMOV.W – else next; Transfer a data block. Starting from the address set in ER5, transfers data ...
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Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of ...
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Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of ...
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Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: * Not available in this LSI. 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains ...
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Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address ...
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Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address ...
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Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Effective Address Calculation PC contents Sign extension Memory contents Memory contents Rev.7.00 Dec. 24, 2008 Page 63 of 698 Effective Address (EA) ...
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Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state the CPU and ...
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Bus-released state Exception handling state RES = High MRES = High Reset state * 1 From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be ...
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Usage Notes 2.9.1 Note on TAS Instruction Usage Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. ...
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The instructions BSET, BCLR, BNOT, BST, and BIST perform the following operations in the order shown: 1. Read data in byte units 2. Perform bit manipulation on the read data according to the instruction 3. Write data in byte units ...
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P17 P16 I/O Output Output P1DDR 1 1 Read value 1 1 The BCLR instruction performs bit manipulation on the read value, which is H'F8 in this example. It clears bit P17 P16 I/O Output Output P1DDR ...
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In order to write to a register containing write-only bits, set aside a work area in memory (in on- chip RAM, for example) and write the data to be manipulated to it. After accessing and manipulating the data in the ...
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P17 P16 I/O Output Output P1DDR 1 1 RAM0 change pin 14 from an output pin to an input pin, the value of bit 4 in P1DDR must be changed from (H'F0 to H'E0). ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting ...
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Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode of this LSI. MDCR ...
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Bit Bit Name Initial Value R/W 7 – – INTM1 0 4 INTM0 0 3 NMIEG 0 2 MRESE 0 1 – RAME 1 Note: * Supported only by the H8S/2218 Group. Description R/W ...
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Operating Mode Descriptions 3.3.1 Mode 4 (Supported Only by the H8S/2218 Group) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function ...
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Mode 6 (Supported Only by the H8S/2218 Group) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A, B and C function as input ports immediately ...
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Pin Functions The pin functions of ports 1, and vary depending on the operating mode. Table 3.2 shows their functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Port 1 P13 ...
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Memory Map in Each Operating Mode Figures 3.1 to 3.4 show the memory map in each operation mode, respectively. ROM: ⎯ RAM: 12 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM desabled) H'000000 External address space ...
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ROM: ⎯ RAM: 12 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM desabled) H'000000 External address space H'C00000 1 USB registers* H'E00000 External address space H'FEE800 2 Reserved* H'FFC000 3 On-chip RAM* H'FFEFC0 External address space H'FFF800 ...
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ROM: ⎯ RAM: 8 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM desabled) H'000000 External address space H'C00000 1 USB registers* H'E00000 External address space H'FEE800 2 Reserved* H'FFD000 3 On-chip RAM* H'FFEFC0 External address space H'FFF800 ...
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HD64F2212, HD64F2212U, HD64F2212CU ROM: 128 kbytes RAM: 12 kbytes Mode 7 (advanced single-chip mode) H'000000 H'000000 On-chip ROM H'00FFFF H'01FFFF H'C00000 H'C00000 USB registers H'DFFFFF H'DFFFFF H'FEE800 H'FEE800 Reserved* H'FFD000 H'FFC000 On-chip RAM H'FFEFBF H'FFEFBF H'FFF800 H'FFF800 Internal I/O registers ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more ...
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Table 4.2 Exception Handling Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace 2 Direct transitions* External interrupt (NMI) Trap instruction # Reserved for system use External interrupt IRQ0 External interrupt IRQ1 External ...
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Reset A reset has the highest exception priority. When the RES or MRES* pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for ...
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Table 4.3 Reset Types Reset Transition Condition MRES Type × Power-on reset Manual reset Low Legend: ×: Don't care A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual ...
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RES, MRES Address bus RD HWR, LWR D15 to D0 (1) (3) Reset exception handling vector address (for power-on reset, (1) = H'000000, (3) = H'000002; for manual reset, (1) = H'000004, (3) = H'000006) (2) (4) Start address ...
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RES, MRES Internal Address bus Internal read signal Internal write signal Internal data bus (1) (3) : Reset exception handling vector address (for a power-on reset, (1) = H'000000, (3) = H'000002 for a manual reset, (1) = H'000004, ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values ...
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Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. 2 (a) Normal Modes* (b) Advanced Modes Notes: 1. Ignored on return. 2. Normal modes are not available ...
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Notes on Use of the Stack When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR ...
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A block diagram of the interrupt controller is shown in figure 5.1. SYSCR NMI input IRQ input Internal interrupt request WOVI to EXIRQ1 Interrupt controller Legend: IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: Interrupt ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected IRQ7 Input Maskable external interrupts IRQ4 Rising, falling, or ...
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Interrupt Priority Registers (IPRA to IPRG, IPRJ, IPRK, IPRM) The IPR registers set priorities (levels for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown ...
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IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. Bit Bit Name Initial Value R/W 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB ...
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Bit Bit Name Initial Value R/W 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 Description R/W IRQ3 Sense Control B R/W IRQ3 Sense Control A 00: Interrupt request generated at ...
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Bit Bit Name Initial Value R/W 1 IRQ0SCB 0 0 IRQ0SCA 0 Legend: ×: Don’t care Notes: 1. IRQ6 is an interrupt only for the on-chip USB. 2. IRQ5 is an interrupt only for the on-chip RTC. 5.3.4 IRQ Status ...
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Interrupt Sources 5.4.1 External Interrupts There are seven external interrupts: NMI, IRQ7, and IRQ4 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. Though IRQ5 is only for the on-chip RTC and IRQ6 ...
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The set timing for IRQnF is shown in figure 5.3. IRQn input pin IRQnF Note The detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. ...
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Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the ...
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Interrupt Origin of Interrupt Source Source TPU channel 2 TGI2A TGI2B TGI2V TGI2U DMAC DEND0A DEND0B DEND1A DEND1B SCI channel 0 ERI0 RXI0 TXI0 TEI0 SCI channel 2 ERI2 RXI2 TXI2 TEI2 USB EXIRQ0 EXIRQ1 Note: * Lower 16 bits ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 5.4 Flowchart of Procedure ...
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Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the CPU and the IPR ...
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Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Rev.7.00 Dec. 24, 2008 Page 106 of 698 REJ09B0074-0700 Program execution status No Interrupt generated? Yes Yes NMI No No ...
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Interrupt Exception Handling Sequence Figure 5.6 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Interrupt Response Times Table 5.4 shows interrupt response times ⎯ the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained ...
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Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch Branch address read Stack manipulation Legend: m: Number of wait states in an external device access. 5.6.5 DMAC Activation by Interrupt The DMAC can be activated ...
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Interrupt request IRQ interrupt On-chip Interrupt source peripheral clear signal module Figure 5.7 Interrupt Control for DMAC Selection of Interrupt Source: An activation factor is directly input to each channel of the DMAC. The activation factors for each channel of ...
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Table 5.6 Interrupt Source Selection and Clearing Control Settings DMAC DTA DMAC Δ 0 Ο 1 Legend: Ο: The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) ...
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Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 ...
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Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is ...
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NMI Interrupt Usage Notes The NMI interrupt is part of the exception processing performed cooperatively by the LSI’s internal interrupt controller and the CPU when the system is operating normally under the specified electrical conditions. No operations, including NMI ...
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Section 6 Bus Controller This LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: ...
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Figure 6.1 shows a block diagram of the bus controller. Chip select signals External bus control signals BREQ* BACK* WAIT* Legend: ABWCR: Bus width control register ASTCR: Access state control register WCRH, WCRL: Waite control registers H, L BCRH, BCRL: ...
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Input/Output Pins Table 6.1 summarizes the pins of the bus controller. These pins are supported only by the H8S/2218 Group. Table 6.1 Pin Configuration Name Symbol AS Address strove RD Read HWR High write LWR Low write Chip select ...
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Register Descriptions The following shows the registers of the bus controller. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register H (WCRH) • Wait control register L (WCRL) • Bus control register ...
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Access State Control Register (ASTCR) ASTCR designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers except for the ...
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Bit Bit Name Initial Value R/W 3 W51 1 2 W50 1 1 W41 1 0 W40 1 Description R/W Area 5 Wait Control 1 and 0 R/W These bits select the number of program wait states when area 5 ...
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WCRL Bit Bit Name Initial Value R/W 7 W31 1 6 W30 1 5 W21 1 4 W20 1 Rev.7.00 Dec. 24, 2008 Page 122 of 698 REJ09B0074-0700 Description R/W Area 3 Wait Control 1 and 0 R/W These ...
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Bit Bit Name Initial Value R/W 3 W11 1 2 W10 1 1 W01 1 0 W00 1 Description R/W Area 1 Wait Control 1 and 0 R/W These bits select the number of program wait states when area 1 ...
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Bus Control Register H (BCRH) BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. This register should be set initial value and not be modified in the H8S/2212 Group. Bit Bit Name ...
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Bus Control Register L (BCRL) BCRL performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. The functions selected by this register are available only in the H8S/2218 Group. This register should not ...
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Pin Function Control Register (PFCR) PFCR performs address output control in external extended mode. When using the USB with the emulator (E6000), enable the A8 and A9 output by setting AE3 to AE0 to 0010. Bit Bit Name Initial ...
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Bus Control 6.4.1 Area Divisions In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for memory and internal I/O registers except for ...
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Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 ⎯ ⎯ 6.4.3 Bus Interface for Each Area The initial state of each ...
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RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. 6.4.4 Chip Select Signals In the H8S/2218 Group chip ...
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Basic Timing The CPU is driven by a system clock (φ), denoted by the symbol φ. The period from one rising edge of φ to the next is referred "state." The memory cycle or bus cycle ...
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Address bus* AS* RD* HWR, LWR* Data bus* Note: * Supported only by the H8S/2218 Group. Figure 6.5 Pin States during On-Chip Memory Access 6.5.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states ...
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Address bus* AS* RD* HWR, LWR* Data bus* Note: * Supported only by the H8S/2218 Group. Figure 6.7 Pin States during On-Chip Peripheral Module Access 6.5.3 External Address Space Access Timing The external address space is accessed with an ...
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Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.6.1 Data Size and Data Alignment (Supported Only by the H8S/2218 Group) Data sizes for the CPU and other internal bus masters are ...
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Byte size Byte size Word size Longword size Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 6.6.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces in the H8S/2218 Group. ...
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Basic Timing 8-Bit 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit 2-state access space in the H8S/2218 Group. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus ...
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Access Space (Except Area 6): Figure 6.11 shows the bus timing for an 8-bit 3- state access space in the H8S/2218 Group. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data ...
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Access Space (Area 6 and RTC): Figure 6.12 shows the bus timing for area 6 and RTC area (address = H'FFFF40 to H'FFFF5F). When the areas are accessed, the data bus cannot be used. Wait states cannot be ...
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Access Space: Figures 6.13 to 6.15 show bus timings for a 16-bit 2-state access space in the H8S/2218 Group. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used ...
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Address bus D15 to D8 Read Write D15 to D8 Note Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.7.00 Dec. 24, 2008 Page 140 of 698 REJ09B0074-0700 Bus ...
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Address bus CSn AS RD D15 to D8 Read HWR LWR Write D15 Note Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) ...
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Access Space: Figures 6.16 to 6.18 show bus timings for a 16-bit 3-state access space in the H8S/2218 Group. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is ...
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Address bus CSn AS RD D15 to D8 Read HWR LWR Write D15 Note Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address ...
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Address bus CSn AS RD D15 to D8 Read HWR LWR Write D15 Note Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) ...