DF2211CUNP24V Renesas Electronics America, DF2211CUNP24V Datasheet - Page 392
DF2211CUNP24V
Manufacturer Part Number
DF2211CUNP24V
Description
MCU 16BIT FLASH 3V 64K 64-QFN
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2218UTF24V.pdf
(758 pages)
Specifications of DF2211CUNP24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Part Number:
DF2211CUNP24V
Manufacturer:
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Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T
the write to the buffer register is not performed. Figure 9.51 shows the timing in this case.
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence. Figure 9.52 shows the operation timing when a TGR compare match is specified
as the clearing source, and H'FFFF is set in TGR.
Rev.7.00 Dec. 24, 2008 Page 336 of 698
REJ09B0074-0700
Figure 9.51 Contention between Buffer Register Write and Input Capture
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 9.52 Contention between Overflow and Counter Clearing
2
TCNT input
clock
TCNT
Counter
clearing signal
TGF flag
TCFV flag
state of a buffer register write cycle, the buffer operation takes precedence and
φ
H'FFFF
Prohibited
Buffer register write cycle
M
Buffer register
T
1
address
N
T
2
H'0000
M
N
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