DF2211CUNP24V Renesas Electronics America, DF2211CUNP24V Datasheet - Page 435

• Manufacturer Part Number: DF2211CUNP24V
• Description: MCU 16BIT FLASH 3V 64K 64-QFN
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2211CUNP24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Bit
3
2
1
0
Bit Name Initial Value R/W
PER
TEND
MPB
MPBT
1. The write value should always be 0 to clear the flag.
2. To clear the flag by the CPU on the HD6432210S, reread the flag after writing 0 to it.
0
1
0
0
R/(W)*
R
R
R/W
1
Description
Parity Error
[Setting condition]
•
[Clearing condition]
•
Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous state
is retained. This bit retains its previous state when the
RE bit in SCR is cleared to 0.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
When a parity error is detected during reception
If a parity error occurs, the receive data is transferred
to RDR but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued
while the PER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
When 0 is written to PER after reading PER = 1*
The PER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
When 0 is written to TDRE after reading TDRE = 1
When the DMAC is activated by a TXI interrupt and
writes data to TDR
Rev.7.00 Dec. 24, 2008 Page 379 of 698
REJ09B0074-0700
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