C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 98
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C8051F019-GQ
Manufacturer Part Number
C8051F019-GQ
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
16
Ram Memory Size
1.25KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1198
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
14.2.
A typical SMBus transaction consists of a START condition, followed by an address byte, one or more bytes of
data, and a STOP condition. The address byte and each of the data bytes are followed by an ACKNOWLEDGE bit
from the receiver. The address byte consists of a 7-bit address plus a direction bit. The direction bit (R/W)
occupies the least-significant bit position of the address. The direction bit is set to logic 1 to indicate a “READ”
operation and cleared to logic 0 to indicate a “WRITE” operation. A general call address (0x00 +R/W) is
recognized by all slave devices allowing a master to address multiple slave devices simultaneously.
All transactions are initiated by the master, with one or more addressed slave devices as the target.
generates the START condition and then transmits the address and direction bit. If the transaction is a WRITE
operation from the master to the slave, the master transmits the data a byte at a time waiting for an
ACKNOWLEDGE from the slave at the end of each byte. If it is a READ operation, the slave transmits the data
waiting for an ACKNOWLEDGE from the master at the end of each byte. At the end of the data transfer, the
master generates a STOP condition to terminate the transaction and free the bus. Figure 14.3 illustrates a typical
SMBus transaction.
The SMBus interface may be configured to operate as either a master or a slave. At any particular time, it will be
operating in one of the following four modes:
14.2.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The first byte transmitted contains the
address of the target slave device and the data direction bit. In this case the data direction bit (R/W) will be logic 0
to indicate a “WRITE” operation. The master then transmits one or more bytes of serial data. After each byte is
transmitted, an acknowledge bit is generated by the slave. To indicate the beginning and the end of the serial
transfer, the master device outputs START and STOP conditions.
14.2.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The first byte is transmitted by the master
and contains the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will
be logic 1 to indicate a “READ” operation. Serial data is then received from the slave on SDA while the master
outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, an
acknowledge bit is transmitted by the master. The master outputs START and STOP conditions to indicate the
beginning and end of the serial transfer.
14.2.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. First, a byte is received that contains an
address and data direction bit. In this case the data direction bit (R/W) will be logic 1 to indicate a “READ”
operation. If the received address matches the slave’s assigned address (or a general call address is received) one or
more bytes of serial data are transmitted to the master. After each byte is received, an acknowledge bit is
transmitted by the master. The master outputs START and STOP conditions to indicate the beginning and end of
the serial transfer.
START
Operation
SLAVE ADDR R/W
ACK
Figure 14.3. SMBus Transaction
DATA
Rev. 1.2
Time
ACK
DATA
C8051F018
C8051F019
NACK
STOP
The master
98