MCF5329CVM240J Freescale Semiconductor, MCF5329CVM240J Datasheet - Page 22

• Manufacturer Part Number: MCF5329CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5329CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
22
1
2
Num
FB4
FB5
FB6
FB7
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see
Timing
The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
Data Input Setup
Data Input Hold
Transfer Acknowledge (TA) Input Setup
Transfer Acknowledge (TA) Input Hold
Characteristics” for SD_CS[3:0] timing.
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
FB_CSn, FB_OE,
Table 9. FlexBus AC Timing Specifications (continued)
FB_BE/BWEn
MCF532x ColdFire
FB_D[31:X]
FB_A[23:0]
FB_CLK
FB_R/W
FB_TS
FB_TA
Characteristic
Figure 7. FlexBus Read Timing
FB1
ADDR[31:X]
®
S0
FB2
Microprocessor Data Sheet, Rev. 5
NOTE
FB6
ADDR[23:0]
S1
DATA
FB4
S2
Symbol
t
t
FB7
t
t
CVFBCH
DVFBCH
FB5
DIFBCH
CIFBCH
Section 5.7.2, “DDR SDRAM AC
S3
FB3
Min
3.5
0
4
0
Freescale Semiconductor
Max
—
—
—
—
Unit
ns
ns
ns
ns