MCF5329CVM240J Freescale Semiconductor, MCF5329CVM240J Datasheet - Page 32

• Manufacturer Part Number: MCF5329CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5329CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
32
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_LD of line.
Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.
Note: LCD_REV toggles in every LCD_HSYN period.
Num
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK
T1
T2
T3
T4
T5
T6
T7
Num
T1
T2
T3
T4
can be programmed as active high or active low. In
mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width
= 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
LCD_LD[15:0]
LCD_HSYNC
LCD_VSYNC
LCD_SPL/LCD_SPR pulse width
End of LCD_LD of line to beginning of LCD_HSYNC
End of LCD_HSYNC to beginning of LCD_LD of line
LCD_CLS rise delay from end of LCD_LD of line
LCD_CLS pulse width
LCD_PS rise delay from LCD_CLS negation
LCD_REV toggle delay from last LCD_LD of line
LCD_LSCLK
LCD_HSYNC to LCD_VSYNC delay
LCD_HSYNC pulse width
LCD_VSYNC to LCD_LSCLK
LCD_LSCLK to LCD_HSYNC
Description
Description
MCF532x ColdFire
T2
Figure 18. Non-TFT Mode Panel Timing
Table 17. Non-TFT Mode Panel Timing
Table 16. Sharp TFT Panel Timing
T1
®
Microprocessor Data Sheet, Rev. 5
T3
Minimum
Figure
—
2
1
1
18, all three signals are active high. When it is in CSTN
Minimum
XMAX
—
1
4
3
1
0
1
Ts
REV_TOGGLE_DELAY+1
HWIDTH + 1
HWAIT2 + 2
HWAIT1 + 1
0 ≤ T3 ≤ Ts
CLS_RISE_DELAY+1
CLS_HI_WIDTH+1
Value
PS_RISE_DELAY
HWAIT2 + 4
HWAIT1+1
T4
Value
1
Freescale Semiconductor
T2
T1
Unit
Tpix
Tpix
Tpix
—
Unit
Ts
Ts
Ts
Ts
Ts
Ts
Ts