MCF5329CVM240J Freescale Semiconductor, MCF5329CVM240J Datasheet - Page 24

• Manufacturer Part Number: MCF5329CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5329CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
24
1
2
3
4
5
6
7
8
Symbol
SD10
SD11
SD12
SD13
The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5329
Reference Manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
SD9
SD_BA[1:0]
SD_RAS
SD_CAS
SD_CLK
SD_CSn
SD_WE
D[31:0]
A[23:0]
SDDM
SD_DQS[3:2] input hold relative to SD_CLK
Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
Data Input Hold relative to SD_CLK (reference only)
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
8
SD4
ROW
CMD
Characteristic
MCF532x ColdFire
Table 10. SDR Timing Specifications (continued)
SD1
SD5
Figure 9. SDR Write Timing
COL
WD1
®
7
Microprocessor Data Sheet, Rev. 5
SD11
SD12
WD2
t
t
t
SDCHDMV
Symbol
t
DQISDCH
SDCHDMI
t
DVSDCH
DISDCH
WD3
SD2
Does not apply. 0.5×SD_CLK fixed width.
SD_CLK
WD4
0.25 ×
Min
1.0
1.5
—
0.75 × SD_CLK
Freescale Semiconductor
+ 0.5
Max
—
—
—
SD3
Unit
ns
ns
ns
ns