HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 100
HD64F3664BPV
Manufacturer Part Number
HD64F3664BPV
Description
MCU 3/5V 32K,PB-FREE 42-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664BPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 4 Address Break
4.1.2
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
4.1.3
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Rev. 6.00 Mar. 24, 2006 Page 70 of 412
REJ09B0142-0600
Bit
7
6
5 to 0
Address Break Status Register (ABRKSR)
Break Address Registers (BARH, BARL)
Break Data Registers (BDRH, BDRL)
Bit Name
ABIF
ABIE
—
Initial
Value
0
0
All 1
R/W
R/W
R/W
—
Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
These bits are always read as 1.
Reserved
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