HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 284

• Manufacturer Part Number: HD64F3664BPV
• Description: MCU 3/5V 32K,PB-FREE 42-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664BPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 I
9. Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock
10. Set the ACKB bit in ICSR to 1 so as to return “No acknowledge” data. Also set the TRS bit in
11. Clear IRIC flag to 0 to release from the Wait State.
12. When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
13. Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the IRIC
14. Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high,
Rev. 6.00 Mar. 24, 2006 Page 254 of 412
REJ09B0142-0600
User processing
(master output)
(master output)
(slave output)
and drives SDA at the 9th receive clock pulse to return an ackowledge signal. Data can be
received continuously by repeating the step [5] to [9].
ICCR to 1 to switch from receive mode to transmit mode.
receive clock pulse.
flag to 0. Clearing of the IRIC flag should be after the WAIT = 0. If the WAIT bit is cleared to
0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition cannot be issued because the output level of the SDA line is fixed as low.
and generates the stop condition.
SDA
SCL
SDA
Master tansmit mode
IRTR
ICDR
IRIC
2
C Bus Interface (IIC)
[1] TRS cleared to 0
Figure 15.6 Master Receive Mode Operation Timing Example (1)
9
A
WAIT set to 1
ACKB cleared to 0
Master receive mode
[2] ICDR read
Bit 7
1
(dummy read)
Bit 6
(MLS = ACKB = 0, WAIT = 1)
2
Bit 5
3
[2] IRIC clearance
Data 1
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
[4] IRIC clearance
[3]
A
9
[5]
[6] ICDR read
Bit 7
Data 1
(Data 1)
1
Bit 6
2
Data 2
[7] IRIC clearance
Bit 5
3
Bit 4
4
Bit 3
5