HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 203

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.3.2
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto-request, external request, and
on-chip module request. The request mode is selected in the RS3–RS0 bits of the DMA channel
control registers 0–3 (CHCR0–CHCR3).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR0–CHCR3 and the DME bit of the
DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0–CHCR3 and the
NMIF and AE bits of DMAOR are all 0).
External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an
external device. Choose one of the modes shown in table 9.3 according to the application system.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,
AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by
either the falling edge or low level of the signal input with the DS bit of CHCR0–CHCR3 (DS = 0
is level detection, DS = 1 is edge detection). The source of the transfer request does not have to be
the data transfer source or destination.
Table 9.3
RS3
0
0
0
Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral
On-Chip Module Request: In this mode a transfer is performed at the transfer request signal
(interrupt request signal) of an on-chip module. The transfer request signals include the receive
data full interrupt (RXI) of the serial communication interface (SCI), the transmit data empty
interrupt (TXI) of the SCI, the input capture A/compare match A interrupt request (IMIA) of the
16-bit integrated-pulse timer (ITU), (table 9.4). When this mode is selected, if the DMA transfer is
enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of
a transfer request signal. The source of the transfer request does not have to be the data transfer
184 RENESAS
module (excluding DMAC)
RS2
0
0
0
DMA Transfer Requests
Selecting External Request Modes with the RS Bits
RS1
0
1
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Single address
mode
Source
Any*
External memory or
memory-mapped
external device
External device with
DACK
Destination
Any*
External device with
DACK
External memory or
memory-mapped
external device