HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 396

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11):
1. Start bit: one 0 bit is output.
2. Transmit data: seven or eight bits are output, LSB first.
3. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
4. Stop bit: one or two 1 bits (stop bits) are output.
5. Mark state: output of 1 bits continues until the start bit of the next transmit data.
6. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the
SCI requests a transmit-data-empty interrupt (TXI) at this time.
from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then
continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-bit data with
TDRE
TEND
Serial
data
request
1
TXI
Start
bit
clears TDRE to 0
0
data in TDR and
handler writes
TXI interrupt
D
0
D
1 frame
1
multiprocessor bit and one stop bit)
Data
D
7
processor
Multi-
bit
0/1
request
TXI
Stop
1
bit
Start
bit
0
D
0
D
1
Data
D
7
processor
Multi-
bit
0/1
request
TEI
Stop
bit
1
Idle (mark
RENESAS 379
state)
1