M30281F8HP#U3B Renesas Electronics America, M30281F8HP#U3B Datasheet - Page 130

• Manufacturer Part Number: M30281F8HP#U3B
• Description: IC M16C/28 MCU FLASH 64K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30281F8HP#U3B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 12.10 Two-phase Pulse (A phase and B phase) and the Z Phase
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0
C
2
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B
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
8
0
0
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “0000
the TAZIE bit in ONSF register to “1” (Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.10 shows
the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
0
G
4
Timer A3
J
TA3
(B phase)
INT2
(Z phase)
NOTES:
TA3
(A phase)
Count source
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1. This timing diagram is for the case where the POL bit in the INT2IC register is set to “1” (rising edge).
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IN
OUT
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3
0
, 1
(1)
0
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2
1
0
0
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7
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1
6
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2 /
f o
m
8
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8
5
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Input equal to or greater than one clock cycle
of count source
1
2
3
4
16
” to the TA3 register and setting
________
5
12. Timer