HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 161
HD64F2318VTE25
Manufacturer Part Number
HD64F2318VTE25
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2318VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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5.4.2
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
interrupt request is sent to the interrupt controller.
bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
the priority system is accepted, and other interrupt requests are held pending.
current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
handling routine starts at the address indicated by the contents of that vector address.
Interrupt Control Mode 0
Rev.7.00 Feb. 14, 2007 page 127 of 1108
Section 5 Interrupt Controller
REJ09B0089-0700
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