HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 686
HD64F2318VTE25
Manufacturer Part Number
HD64F2318VTE25
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2318VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 17 ROM
Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2319 F-ZTAT chip
measures the low period of the asynchronous SCI communication data (H'00) transmitted
continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1
stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the
measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate
adjustment. The host should confirm that this adjustment end indication (H'00) has been received
normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally,
initiate boot mode again (reset), and repeat the above operations. Depending on the host’s
transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between
the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate
should be set to 9,600 or 19,200 bps.
Table 17.31 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 17.31 System Clock Frequencies for Which Automatic Adjustment of H8S/2319
Host Bit Rate
19,200 bps
9,600 bps
Rev.7.00 Feb. 14, 2007 page 652 of 1108
REJ09B0089-0700
F-ZTAT Bit Rate Is Possible
Start
bit
Figure 17.42 Automatic SCI Bit Rate Adjustment
D0
System Clock Frequency for Which Automatic Adjustment
of H8S/2319 F-ZTAT Bit Rate Is Possible
16 MHz to 25 MHz
8 MHz to 25 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
D5
D6
D7
(1 or more bits)
High period
Stop
bit
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