HD64F2318VTE25 Renesas Electronics America, HD64F2318VTE25 Datasheet - Page 313
HD64F2318VTE25
Manufacturer Part Number
HD64F2318VTE25
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2318VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Port E Data Register (PEDR)
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to
PE0).
PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port E Register (PORTE)
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as
PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
PE7DR
R/W
PE7
— *
R
7
0
7
PE6DR
R/W
PE6
— *
R
6
0
6
PE5DR
R/W
PE5
— *
R
5
0
5
PE4DR
R/W
PE4
— *
R
4
0
4
Rev.7.00 Feb. 14, 2007 page 279 of 1108
PE3DR
R/W
PE3
— *
R
3
0
3
PE2DR
R/W
PE2
— *
R
2
0
2
Section 8 I/O Ports
PE1DR
REJ09B0089-0700
R/W
PE1
— *
R
1
0
1
PE0DR
R/W
PE0
— *
R
0
0
0
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