M308A5SGP#U5 Renesas Electronics America, M308A5SGP#U5 Datasheet - Page 67

• Manufacturer Part Number: M308A5SGP#U5
• Description: MCU ROMLESS 12K RAM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M308A5SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 81
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 18x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M32C/8A Group
REJ03B0213-0111 Rev.1.11 Mar 31, 2009
Page 65 of 66
Figure 5.10
WR,WRL,WRH
Microprocessor Mode
ADi /DBi
(when accessing an external memory space with the multiplexed bus)
ADi /DBi
Write Timing (2φ + 2 φ Bus Cycle)
BCLK
BCLK
BHE
BHE
ADi
ADi
ALE
RD
ALE
CSi
CSi
Read Timing (2φ + 2 φ Bus Cycle)
NOTES:
NOTES:
1. Varies with operation frequency:
1. Varies with operation frequency:
td(BCLK-ALE)
18ns.max
td(BCLK-ALE)
18ns.max
VCC1 = VCC2 = 3.3 V Timing Diagram (4)
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + b φ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + b φ, n = a)
th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min
th(WR-DB) = (tcyc / 2 - 20) ns.min
td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a φ + b φ, m = (b x 2) - 1)
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + b φ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + b φ, n = a)
th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + b φ, m = (b x 2) - 1)
tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a φ + b φ, p = {(a + b - 1) x 2} + 1)
tcyc=
td(BCLK-AD)
18ns.max
td(BCLK-CS)
18ns.max
td(BCLK-AD)
18ns.max
td(BCLK-CS)
18ns.max
td(AD-ALE)
td(AD-ALE)
f(BCLK)
tac2(AD-DB)
10
9
(2)
(1)
Address
Address
(1)
th(BCLK-ALE)
-2ns.min
th(BCLK-ALE)
-2ns.min
th(ALE-AD)
th(ALE-AD)
(2)
(1)
td(BCLK-RD)
18ns.max
td(BCLK-WR)
18ns.max
tdz(RD-AD)
8ns.max
Measurement Conditions:
- VCC1 = VCC2 = 3.0 to 3.6 V
- Input high and low voltage VIH = 1.5 V, VIL = 0.5 V
- Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
tac2(RD-DB)
tcyc
tcyc
td(DB-WR)
th(BCLK-WR)
0ns.min
(1)
Data output
tsu(DB-BCLK) 30ns.min
th(BCLK-RD)
-3ns.min
th(WR-CS)
(2)
Data input
VCC1=VCC2=3.3V
th(RD-CS)
(2)
5. Electrical Characteristics
th(WR-DB)
th(RD-AD)
th(RD-DB) 0ns.min
(1)
th(WR-AD)
(1)
(2)
th(BCLK-AD)
0ns.min
t
0ns.min
Address
th(BCLK-CS)
0ns.min
h(BCLK-CS)
Address
th(BCLK-AD)
0ns.min
(2)