M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 148

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 16.11 Serial I/O-related registers (7)
1 .
0
C
9
0 .
8 /
B
0
UARTi special mode register 2
b7
0
0
1
A
8
G
b6
u
7
o r
. g
0 -
b5
u
1
0
p
0
, 2
b4
0
2
0
b3
0
5
b2
Page 135
b1
b0
symbol
SWC2 SCL wait output bit 2
SHTC Start/stop condition
IICM2
SWC
SDHI
CSC
STC
ALS
Bit
f o
UiSMR2 (i=2 to 4)
3
Symbol
2
9
SCL wait output bit
SDA output stop flag
UARTi initialize bit
SDA output inhibit bit
control bit
IIC mode select bit 2
Clock synchronous bit
Bit name
0336
16
, 0326
Address
0 : NACK/ACK interrupt
1 : UART transfer/receive interrupt
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : UARTi clock
1 : 0 output
0 : Enabled
1 : Disabled (high impedance)
Must set to "1" in selecting IIC mode.
DMA source - ACK
Transfer to receive buffer at the rising edge of
last bit of receive clock
Receive interrupt is occurred at the rising
edge of last bit of receive clock
DMA source - UART receive
Transfer to receive buffer at the falling edge
of last bit of receive clock
Receive interrupt is occurred at the falling
edge of last bit of receive clock
16
, 02F6
16
When reset
00
Function
16
16. Serial I/O
R
W