M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 230

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
1 .
0
C
(4) External interrupt
• Edge sense
• Level sense
• When the polarity of the INT
9
Figure 27.2 Switching condition of INT interrupt request
0 .
8 /
B
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
0
0
0
Interrupt_C:
to INT
input to pins INT
mode, at least 250 ns width is necessary.)
After changing the polarity, set the interrupt request bit to "0". Figure 27.2 shows the procedure for
changing the INT interrupt generate factor.
1
A
G
8
u
7
o r
pushm R0,R1,R2,R3,A0,A1
fset
••••
••••
popm R0,R1,R2,R3,A0,A1
fclr
pushm R0
mov.w 6[SP],R0
ldc
popm R0
nop
reit
. g
0 -
u
1
0
5
p
0
, 2
0
regardless of the CPU operation clock.
2
0
Interrupt C routine
I
U
R0,FLG
0
5
______
Page 217
0
to INT
5
f o
regardless of the CPU operation clock. (When X
0
to INT
3
(Enable the accepting of INT interrupt request)
2
Set the interrupt priority level to level 1 to 7
9
Set the interrupt priority level to level 0
Clear the interrupt request bit to “0”
5
______
pins is changed, the interrupt request bit is sometimes set to "1".
; Store registers
; Multiple interrupt enabled
;Restore registers
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
; Read FLG on stack
; Set in FLG
; Restore R0 register
; Dummy
; Interrupt completed
Set the polarity select bit
(Disable
INT
interrupt)
IN
=20MHz and no division
27. Usage Precaution
0