D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 720
D12332VFC25
Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of D12332VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25
HD6412332VFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses
the same processing procedure as for the normal SCI. Figure 15.7 shows an example of the
transmission processing flow.
[1] Perform smart card interface mode initialization as described above in Initialization.
[2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the
[3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1.
[4] Read the receive data from RDR.
[5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2].
[6] To end reception, clear the RE bit to 0.
Rev.4.00 Sep. 07, 2007 Page 688 of 1210
REJ09B0245-0400
appropriate receive error handling, then clear both the ORER and the PER flag to 0.
No
No
Figure 15.7 Sample Reception Flowchart
RDRF flag in SSR to 0
Read RDR and clear
All data received?
Start of reception
Clear RE bit to 0
ORER = 0 and
Initialization
RDRF = 1?
PER = 0?
Start
Yes
Yes
Yes
No
Error handling
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