COP8CCE9IMT9/NOPB National Semiconductor, COP8CCE9IMT9/NOPB Datasheet - Page 3

• Manufacturer Part Number: COP8CCE9IMT9/NOPB
• Description: IC MCU EEPROM 8BIT 8K 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCE9IMT9/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Data Ram Size: 256 B
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: *COP8CCE9IMT9; *COP8CCE9IMT9/NOPB; COP8CCE9IMT9

1.0 General Description ..................................................................................................................................... 1
2.0 Features ....................................................................................................................................................... 1
3.0 Block Diagram .............................................................................................................................................. 2
4.0 Ordering Information .................................................................................................................................... 2
5.0 Connection Diagrams ................................................................................................................................... 6
6.0 Architectural Overview ................................................................................................................................. 8
7.0 Absolute Maximum Ratings ....................................................................................................................... 10
8.0 Electrical Characteristics ............................................................................................................................ 10
9.0 Pin Descriptions ......................................................................................................................................... 17
10.0 Functional Description .............................................................................................................................. 19
11.0 In-System Programming ........................................................................................................................... 27
12.0 Timers ....................................................................................................................................................... 34
6.1 EMI REDUCTION ...................................................................................................................................... 8
6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ........................................................................ 8
6.3 DUAL CLOCK AND CLOCK DOUBLER ................................................................................................... 8
6.4 TRUE IN-SYSTEM EMULATION .............................................................................................................. 8
6.5 ARCHITECTURE
6.6 INSTRUCTION SET ................................................................................................................................. 8
6.7 PACKAGING/PIN EFFICIENCY ................................................................................................................ 9
9.1 EMULATION CONNECTION ................................................................................................................... 18
10.1 CPU REGISTERS ................................................................................................................................. 19
10.2 PROGRAM MEMORY ........................................................................................................................... 19
10.3 DATA MEMORY .................................................................................................................................... 19
10.4 DATA MEMORY SEGMENT RAM EXTENSION .................................................................................. 20
10.5 OPTION REGISTER ............................................................................................................................. 21
10.6 SECURITY ............................................................................................................................................ 21
10.7 RESET ................................................................................................................................................... 22
10.8 OSCILLATOR CIRCUITS ...................................................................................................................... 25
10.9 CONTROL REGISTERS ....................................................................................................................... 26
11.1 INTRODUCTION ................................................................................................................................... 27
11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 27
11.3 REGISTERS .......................................................................................................................................... 27
11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 29
11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 29
11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 30
11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 30
11.8 USER ISP AND VIRTUAL E
11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM ....................... 33
11.10 FLASH MEMORY DURABILITY CONSIDERATIONS ........................................................................ 33
12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 34
6.6.1 Key Instruction Set Features ............................................................................................................... 8
6.6.2 Single Byte/Single Cycle Code Execution
6.6.3 Many Single-Byte, Multi-Function Instructions .................................................................................... 8
6.6.4 Bit-Level Control .................................................................................................................................. 9
6.6.5 Register Set ......................................................................................................................................... 9
10.4.1 Virtual EEPROM .............................................................................................................................. 21
10.7.1 External Reset ................................................................................................................................. 23
10.7.2 On-Chip Brownout Reset ................................................................................................................. 23
10.8.1 Oscillator .......................................................................................................................................... 25
10.8.2 Clock Doubler .................................................................................................................................. 26
10.9.1 CNTRL Register (Address X'00EE) ................................................................................................. 26
10.9.2 PSW Register (Address X'00EF) ..................................................................................................... 26
10.9.3 ICNTRL Register (Address X'00E8) ................................................................................................ 26
10.9.4 T2CNTRL Register (Address X'00C6) ............................................................................................. 26
10.9.5 HSTCR Register (Address X'00AF) ................................................................................................ 26
10.9.6 ITMR Register (Address X'00CF) .................................................................................................... 26
10.9.7 ENAD Register (Address X'00CB) .................................................................................................. 27
11.3.1 ISP Address Registers ..................................................................................................................... 27
11.3.2 ISP Read Data Register .................................................................................................................. 28
11.3.3 ISP Write Data Register ................................................................................................................... 28
11.3.4 ISP Write Timing Register ................................................................................................................ 28
12.1.1 ITMR Register .................................................................................................................................. 34
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Table of Contents
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