MCF5280CVF66J Freescale Semiconductor, MCF5280CVF66J Datasheet - Page 287

• Manufacturer Part Number: MCF5280CVF66J
• Description: IC MPU RISC 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Accesses in synchronous burst page mode always cause the following sequence:
15.2.3.5 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is responsible for
providing timing and control to refresh the SDRAM without user interaction. Once the refresh counter is
set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh request flag is set
and the counter begins counting down again. The DRAM controller completes any active burst operation
and then performs a
refresh request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command,
the auto-refresh command, and then a delay until any
initiated during the auto-refresh cycle is delayed until the cycle is completed.
Freescale Semiconductor
SDRAM_CS[0] or [1]
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
ACTV
NOP
commands).
size.
PALL
CLKOUT
DRAMW
commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
command
D[31:0]
BS[3:0]
command
A[23:0]
SRAS
SCAS
PALL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
t
CASL
ACTV
operation. The DRAM controller then initiates a refresh cycle and clears the
READ
Row
= 2
Figure 15-7. Burst Write SDRAM Access
NOP
NOP
or
WRITE
Column
commands to assure the
WRITE
commands to service the transfer size with the given port
Column Column
WRITE
ACTV
WRITE
command is allowed. Any SDRAM access
t
RWL
ACTV
WRITE
-to-precharge delay.
ACTV
Column
NOP
Synchronous DRAM Controller Module
delay.
PALL
t
RP
NOP
15-15