MCF5280CVF66J Freescale Semiconductor, MCF5280CVF66J Datasheet - Page 487
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MCF5280CVF66J
Manufacturer Part Number
MCF5280CVF66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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25.4.11.3 Auto-Power Save Mode
Auto-power save mode enables normal operation with optimized power savings. Once the auto-power
save (APS) bit in CANMCR is set, the FlexCAN looks for a set of conditions in which there is no need for
its clocks to be running. If these conditions are met, the FlexCAN stops its clocks, thus saving power. The
following conditions will activate auto-power save mode.
While its clocks are stopped, if the FlexCAN senses that any one of the aforementioned conditions is no
longer true, it restarts its clocks. The FlexCAN then continues to monitor these conditions and
stops/restarts its clocks accordingly.
25.4.12 Interrupts
The module can generate up to 19 interrupt sources (16 interrupts due to message buffers and 3 interrupts
due to Bus-off, Error and Wake-up). Each one of the message buffers can be an interrupt source, if its
corresponding IMASK bit is set.
There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the
buffer is initialized for either transmission or reception, and thus its interrupt routine can be fixed at
compilation time. Each of the buffers is assigned a bit in the IFLAG register. The bit is set when the
corresponding buffer completes a successful transmission or reception, and cleared when the CPU reads
the interrupt flag register (IFLAG) while the associated bit is set, and then writes it back as ‘1’ (and no new
event of the same type occurs between the read and the write actions).
The other 3 interrupt sources (Bus-off, Error and Wake-up) act in the same way, and are located in the Error
& Status register. The Bus-off and Error interrupt mask bits are located in the CANCTRL0 register, and
the Wake-up interrupt mask bit is located in the CANMCR.
25.5
This section describes the registers in the FlexCAN module.
Programming the FlexCAN control registers is typically done during system initialization, prior to the
FlexCAN becoming synchronized with the CAN bus. The configuration registers can be changed after
synchronization by halting the FlexCAN module. This is done when the user sets the HALT bit in the
FlexCAN module configuration register (CANMCR). The FlexCAN responds by setting the
CANMCR[NOTRDY] bit. Additionally, the control registers can be modified while the MCU is in
background debug mode.
Freescale Semiconductor
•
•
•
•
No Rx/Tx frame in progress.
No transfer of Rx/Tx frames to and from an SMB, and no Tx frame awaiting transmission in any
message buffer.
No CPU access to the FlexCAN module.
The FlexCAN is not in debug mode, low-power stop mode, or the bus off state.
Programmer’s Model
The FlexCAN has no hard-wired protection against invalid bit/field
programming within its registers. Specifically, no protection is provided if
the programming does not meet CAN protocol requirements.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE
FlexCAN
25-17
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