R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 197

MCU 384+8KB FLASH 40K 144-LQFP

R5F64175DFD#U0

Manufacturer Part Number
R5F64175DFD#U0
Description
MCU 384+8KB FLASH 40K 144-LQFP
Manufacturer
Renesas Electronics America
Series
M16C/R32C/100/117r
Datasheet

Specifications of R5F64175DFD#U0

Core Processor
R32C/100
Core Size
16/32-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
120
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F64175DFD#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F64175DFD#U0R5F64175DFD#UB
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
Figure 13.11 Source-read Bus Cycles in a Transfer Cycle
(1) One bus cycle of source-read is generated
(2) Two bus cycles of source-read are generated
(3) One bus cycle of source-read is generated with one wait cycle
(4) Two bus cycles of source-read is generated with one wait cycle
Example: 16-bit data transfer from the address 8n of the RAM
CPU clock
CPU address bus
CPU data bus
CPU RD signal
CPU WR signal
CPU clock
CPU address bus
CPU data bus
CPU RD signal
CPU WR signal
CPU clock
CPU address bus
CPU data bus
CPU RD signal
CPU WR signal
CPU clock
CPU address bus
CPU data bus
CPU RD signal
CPU WR signal
Note:
Example: 16-bit data transfer from the address 16n+7 of the ROM
Example: 16-bit data transfer from the address 8n+7 of the RAM
Example: 16-bit data transfer from the address 16n of the ROM
1. The above applies under the condition of one bus cycle of destination-write. In real cases, the number of
destination-write bus cycles should be considered according to the conditions such as above.
Rev.1.10
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
DSA
DSA
DSA
DSA
[DSA] [DDA]
[DSA]
DSA+1
DDA
[DSA]
[DSA]
[DSA+1]
DDA
DDA
DSA+1
[DDA]
[DDA]
[DSA+1]
DDA
CPU occupied
[DDA]
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
CPU occupied
Page 180 of 604
13. DMAC

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