R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 430

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
Table 25.3
Note:
Mailboxes [0] to [23]
Mailboxes [24] to [27]
Mailboxes [28] to [31]
25.1.1.5
25.1.1.6
1.
When the MBM bit is 0 (normal mailbox mode), mailboxes [0] to [31] are configured as transmit or
receive mailboxes.
When this bit is 1 (FIFO mailbox mode), mailboxes [0] to [23] are configured as transmit or receive
mailboxes. Mailboxes [24] to [27] are configured as a transmit FIFO and mailboxes [28] to [31] as a
receive FIFO.
Transmit data is written into mailbox [24] (mailbox [24] is a window mailbox for the transmit FIFO).
Receive data is read from mailbox [28] (mailbox [28] is a window mailbox for the receive FIFO).
Table 25.3 lists the mailbox configuration.
The IDFM bit specifies the ID format.
When this bit is 00b, all mailboxes (including FIFO mailboxes) handle only standard IDs.
When this bit is 01b, all mailboxes (including FIFO mailboxes) handle only extended IDs.
When this bit is 10b, all mailboxes (including FIFO mailboxes) handle both standard IDs and extended
IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in
normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for
mailboxes [0] to [23], the IDE bit in registers C0FIDCR0 and C0FIDCR1 is used for the receive FIFO,
and the IDE bit in mailbox [24] is used for the transmit FIFO.
Do not set 11b to the IDFM bit.
When the MBM bit is set to 1, note the following:
• Transmit FIFO is controlled by the C0TFCR register.
• Receive FIFO is controlled by the C0RFCR register.
• Refer to the C0MIER register about the FIFO interrupts.
• The corresponding bits in the C0MKIVLR register for mailboxes [24] to [31] are disabled. Set 0 to
• Transmit/receive FIFOs can be used for both data frames and remote frames.
Mailbox
The C0MCTLj register (j = 0 to 31) for mailboxes [24] to [27] is disabled.
Registers C0MCTL24 to C0MCTL27 cannot be used.
The C0MCTLj register for mailboxes [28] to [31] is disabled.
Registers C0MCTL28 to C0MCTL31 cannot be used.
these bits.
MBM Bit
Mailbox Configuration
IDFM Bit
Rev.1.10
Normal mailbox
(Normal Mailbox Mode)
MBM = 0
Normal mailbox
Transmit FIFO
Receive FIFO
(FIFO Mailbox Mode)
MBM = 1
(1)
25. CAN Module
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