R5F64175DFD#U0 Renesas Electronics America, R5F64175DFD#U0 Datasheet - Page 287

• Manufacturer Part Number: R5F64175DFD#U0
• Description: MCU 384+8KB FLASH 40K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C/R32C/100/117r

Specifications of R5F64175DFD#U0

• Core Processor: R32C/100
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 120
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R32C/117 Group
REJ09B0533-0110
Sep 08, 2010
18.1.3
Figure 18.23 Bit Order (i = 0 to 8)
18.1.4
Case 1: When the UFORM bit in the UiC0 register is set to 0 (LSB first)
Case 2: When the UFORM bit in the UiC0 register is set to 1 (MSB first)
As shown in Figure 18.23, the bit order is selected using the UFORM bit in the UiC0 register (i = 0 to 8).
In continuous receive mode, data reception is automatically enabled by a read access to the receive
buffer register without any write of dummy data to the transmit buffer register. To start data reception,
however, dummy data is required to read the receive buffer register.
When the UiRRM bit (i = 0 to 8) in registers U0C1 to U6C1 and U78CON is set to 1 (continuous receive
mode enabled), the TI bit in the UiC1 register is set to 0 (data held in the UiTB register) by a read
access to the UiRB register. In this UiRRM bit setting, any dummy data should not be written to the
UiTB register.
Note:
Note:
LSB First and MSB First Selection
Continuous Receive Mode
1. The figure above applies under the following conditions:
2. The figure above applies under the following conditions:
RXDi
RXDi
CLKi
TXDi
CLKi
TXDi
-The CKPOL bit in the UiC0 register = 0 (transmitted data output on the falling edge of the transmit/
-The UiLCH bit in the UiC1 register = 0 (data is non logic-inverted)
-The CKPOL bit in the UiC0 register = 0 (transmitted data output on the falling edge of the transmit/
-The UiLCH bit in the UiC1 register = 0 (data is non logic-inverted)
receive clock and received data input on the rising edge)
receive clock and received data input on the rising edge)
Rev.1.10
D0
D0
D7
D7
D1
D1
D6
D6
D2
D2
D5
D5
D3
D3
D4
D4
D4
D4
D3
D3
D5
D5
D2
D2
D6
D6
D1
D1
D7
D7
D0
D0
18. Serial Interface
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