DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 478
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 478 of 1208
- Download datasheet (8Mb)
Section 8 EXDMA Controller (EXDMAC)
Rev.7.00 Mar. 18, 2009 page 410 of 1136
REJ09B0109-0700
φ pin
EDREQ
EDRAK
EDREQ
acceptance
internal
processing
state
Bus cycle
EDACK
φ pin
EDREQ
EDRAK
Bus cycle
CPU
operation
EDACK
ETEND
CPU cycle
Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
External
space
(No Contention/Single Address Mode/Falling Edge Sensing)
Bus release
Edge confirmation
Start of transfer
processing
CPU cycle CPU cycle
External
(CPU Cycles/Single Address Mode/Low Level Sensing)
space
External
space
Start of high
level sensing
EXDMA single
transfer cycle
External
EXDMA single
space
transfer cycle
Edge confirmation
Start of transfer
processing
Bus release
CPU cycle CPU cycle
2 bus cycles
EXDMA single
Start of high
level sensing
transfer cycle
External
space
Edge confirmation
Start of transfer
processing
Last transfer cycle
Bus release
External
EXDMA single
space
transfer cycle
Start of high
level sensing
EXDMA single
transfer cycle
CPU cycle
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