DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 610
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 610 of 1208
- Download datasheet (8Mb)
Section 10 I/O Ports
10.16.2 Port H Data Register (PHDR)
PHDR stores output data for the port H pins.
Bit
7
to
4
3
2
1
0
10.16.3 Port H Register (PORTH)
PORTH shows port H pin states.
PORTH cannot be modified.
Bit
7
to
4
3
2
1
0
Note:
Rev.7.00 Mar. 18, 2009 page 542 of 1136
REJ09B0109-0700
Bit Name
⎯
PH0DR
Bit Name
⎯
PH3DR
PH2DR
PH1DR
PH3
PH2
PH1
PH0
* Determined by the states of pins PH3 to PH0.
Initial Value
All 0
0
Initial Value
Undefined
0
0
0
⎯*
⎯*
⎯*
⎯*
R/W
⎯
R/W
R/W
⎯
R/W
R/W
R/W
R
R
R
R
Description
Reserved
These bits are reserved; they are always read as 0
and cannot be modified.
Description
Reserved
If these bits are read, they will return an undefined
value.
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
If a port H read is performed while PHDDR bits are
set to 1, the PHDR values are read. If a port H read
is performed while PHDDR bits are cleared to 0, the
pin states are read.
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