DF2370RVFQ34V Renesas Electronics America, DF2370RVFQ34V Datasheet - Page 57
![IC H8S/2370 MCUFLSH 256K 144LQFP](/photos/12/41/124197/df2370rvfq34v_sml.jpg)
DF2370RVFQ34V
Manufacturer Part Number
DF2370RVFQ34V
Description
IC H8S/2370 MCUFLSH 256K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 57 of 1208
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Figure 18.2 Block Diagram of D/A Converter for H8S/2375, H8S/2375R, H8S/2373,
Figure 18.3 Example of D/A Converter Operation..................................................................... 830
Section 20 Flash Memory (0.35-μm F-ZTAT Version) ....................................833
Figure 20.1 Block Diagram of Flash Memory........................................................................... 834
Figure 20.2 Flash Memory State Transitions.............................................................................. 835
Figure 20.3 Boot Mode............................................................................................................... 836
Figure 20.4 User Program Mode ................................................................................................ 837
Figure 20.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)....................... 839
Figure 20.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 849
Figure 20.7 Program/Program-Verify Flowchart ....................................................................... 851
Figure 20.8 Erase/Erase-Verify Flowchart ................................................................................. 853
Figure 20.9 Power-On/Off Timing ............................................................................................. 858
Figure 20.10 Mode Transition Timing
Section 21 Flash Memory (0.18-μm F-ZTAT Version) ....................................861
Figure 21.1 Block Diagram of Flash Memory............................................................................ 863
Figure 21.2 Mode Transition of Flash Memory.......................................................................... 864
Figure 21.3 Flash Memory Configuration .................................................................................. 866
Figure 21.4 Block Division of User MAT .................................................................................. 867
Figure 21.5 Overview of User Procedure Program .................................................................... 868
Figure 21.6 System Configuration in Boot Mode....................................................................... 892
Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 892
Figure 21.8 Overview of Boot Mode State Transition Diagram................................................. 894
Figure 21.9 Programming/Erasing Overview Flow.................................................................... 895
Figure 21.10 RAM Map when Programming/Erasing Is Executed .............................................. 896
Figure 21.11 Programming Procedure.......................................................................................... 897
Figure 21.12 Erasing Procedure ................................................................................................... 904
Figure 21.13 Procedure for Programming User MAT in User Boot Mode .................................. 907
Figure 21.14 Procedure for Erasing User MAT in User Boot Mode ............................................ 909
Figure 21.15 Transitions to Error-Protection State....................................................................... 922
Figure 21.16 Switching between the User MAT and User Boot MAT ........................................ 923
Figure 21.17 Boot Program States................................................................................................ 925
Figure 21.18 Bit-Rate-Adjustment Sequence ............................................................................... 926
Figure 21.19 Communication Protocol Format ............................................................................ 927
Figure 21.20 New Bit-Rate Selection Sequence........................................................................... 938
Figure 21.21 Programming Sequence........................................................................................... 942
Figure 21.22 Erasure Sequence .................................................................................................... 945
and H8S/2373R ....................................................................................................... 823
(Example: Boot Mode → User Mode ↔ User Program Mode).............................. 859
Rev.7.00 Mar. 18, 2009 page lv of lxvi
REJ09B0109-0700
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