HD64F2239FA16 Renesas Electronics America, HD64F2239FA16 Datasheet - Page 339

• Manufacturer Part Number: HD64F2239FA16
• Description: IC H8S MCU FLASH 384K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239FA16

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
8.7.2
When the MSTPA7 bit in MSTPCRA is set to 1, the DMAC clock stops, and the module stop
state is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
8.7.3
When the DTA bit is cleared to 0, the internal interrupt signal that is specified for the DMAC
transfer source is detected at the edge. In medium-speed mode, the DMAC operates by the
medium-speed clock and the internal peripheral module operates by the high-speed clock.
Therefore, when the corresponding interruption source is cleared by the CPU, DTC, or other
channels of the DMAC and the period until the next interruption is executed is less than one state
regarding to the DMAC clock (bus master clock), the signal is not detected at the edge and
ignored.
register is read as shown in figure 8.39.
DMA internal
address
DMA register
operation
DMA control
Module Stop
Medium-Speed Mode
Figure 8.39 Contention between DMAC Register Update and CPU Read
Note: The lower word of MAR is the updated value after the operation in [1].
φ
MAR upper
word read
Idle
CPU longword read
MAR lower
word read
[1]
Transfe
source
Read
Rev. 6.00 Mar. 18, 2010 Page 277 of 982
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
Section 8 DMA Controller (DMAC)
DMA write
Idle
REJ09B0054-0600