HD64F2239FA16 Renesas Electronics America, HD64F2239FA16 Datasheet - Page 348

• Manufacturer Part Number: HD64F2239FA16
• Description: IC H8S MCU FLASH 384K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239FA16

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 Data Transfer Controller (DTC)
9.2.7
DTCER is a set of registers to specify the DTC activation interrupt source, and comprised of eight
registers; DTCERA to DTCERG, and DTCERI. The correspondence between interrupt sources
and DTCE bits, and vector numbers generated by the interrupt controller are shown in table 9.2.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. When multiple activation sources are to be set at one time, only at the initial setting,
writing data is enabled after executing a dummy read on the relevant register with all the interrupts
being masked.
Note: n = A to G, and I
Rev. 6.00 Mar. 18, 2010 Page 286 of 982
REJ09B0054-0600
Bit
7
6
5
4
3
2
1
0
DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI)
Bit Name
DTCEn7
DTCEn6
DTCEn5
DTCEn4
DTCEn3
DTCEn2
DTCEn1
DTCEn0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DTC Activation Enable
0: Disables an interrupt for DTC activation.
1: Specifies a relevant interrupt source as a DTC
[Clearing conditions]
•
•
[Retaining condition]
When the DISEL bit is 0 and the specified number
of transfers have not been completed
activation source.
When the DISEL bit in MRB is 1 and the data
transfer has ended
When the specified number of transfers have
ended