MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 199

• Manufacturer Part Number: MCF5272VF66R2J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66R2J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

9.6
Each SDRAM requires an initialization sequence before it can be accessed. After power up, the SDRAM
requires a certain time (100 µS) before it can accept the first command of the initialization procedure. After
this time, one
an
SDRAM device mode register.
SDRAM mode register data is transferred on the address signals, so all SDRAM devices are configured
simultaneously.
Initialization is enabled by setting SDCR[INIT] and performing a dummy write to the SDRAM address
space. The SDRAM controller executes the required
automatically loads the mode register, which configures the SDRAM as follows:
SDCR[ACT] is set after initialization.
9.7
The SDRAM can be powered down by setting SDCR[GSL]. The SDRAM controller executes the required
power-down command sequence to ensure self-refresh during power down. The SDRAM controller
completes the current memory access then automatically issues the following commands to force the
SDRAM into sleep mode:
In self-refresh mode, SDRAM devices can refresh themselves without an external clock. After
power-down completes, SDCR[SLEEP] is set, the SDRAM clock output is driven high, and SDCLKE is
driven low.
Freescale Semiconductor
Bits
3–2
1–0
INITIATE LOAD REGISTER SET
•
•
SDRAM internal burst is always disabled.
CAS latency is defined by SDTR[CLT].
precharge all banks
nop
auto refresh command
Name
RCD
Auto Initialization
Power-Down and Self-Refresh
CLT
PRECHARGE ALL
RAS-to-CAS delay. The reset value is 1, requiring 2 clock cycles for SDRAM activation.
00 1 cycle
01 2 cycles (default)
10 3 cycles
11 4 cycles
CAS latency. Specifies the delay programmed into the SDRAM mode register during initialization, indicating
the time between a
SDRAM controller uses this value to sequence its state machine during read operations. CLT cannot be
changed after the mode register is written.
00 Reserved
01 2-cycle CAS latency (default)
1x Reserved
MCF5272 ColdFire
Table 9-8. SDTR Field Descriptions (continued)
command and eight
command is executed, which writes the SDRAM configuration into the
READ
command being issued to the SDRAM and data appearing on the pins. The
®
Integrated Microprocessor User’s Manual, Rev. 3
REFRESH
PRECHARGE
Description
commands are required. After initialization,
and
REFRESH
commands and
SDRAM Controller
9-9