MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 242
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Ethernet Module
11.5.14 Maximum Frame Length Register (MFLR)
As shown in
MAX_FL field. The MAX_FL field allows the user to program the maximum legal-size frame. Frames
larger than this size cause the BABT interrupt (transmit frames) or BABR interrupt and receive buffer
descriptor LG bit to be asserted (receive frames). Frames exceeding the MAX_FL are not truncated.
Bits 31–24 provide an eight-bit read-only field that provides address recognition information from the
receive block about the frame currently being received by the FEC.
Table 11-21
11-24
29–24
23–11
10–0
Bits
31
30
Reset
Reset
Field BRDCAST MULTCAST
Field
Addr
R/W
R/W
MULTCAST
BRDCAST
MAX_FL
describes the MFLR fields.
Figure
HASH
Name
31
15
—
11-18, the MFLR register serves two purposes. Bits 10–0 provide the user R/W
MCF5272 ColdFire
Broadcast address received. Set if the current receive frame contained a destination address of all
ones (the broadcast address). Cleared if the current receive frame does not correspond to a
broadcast address.
Multicast address received. Set if the current receive frame contained a multi-cast destination
address (the least significant bit of the DA was set). Cleared if the current receive frame does not
correspond to a multi-cast address.
Current hash value. Corresponds to the hash value of the current receive frame’s destination
address. The hash value is a 6-bit field extracted from the least significant portion of the CRC
register.
Reserved, should be cleared.
Maximum frame length. Length is measured starting at DA and includes the CRC at the end of the
frame. Transmit frames longer than MAX_FL cause the BABT interrupt to occur. Receive frames
longer than MAX_FL cause the BABR interrupt to occur and set the LG bit in the end-of-frame buffer
descriptor. Frames exceeding the MAX_FL are not truncated. Transmit frames are never truncated,
but receive frames are truncated at 2k-1 bytes. The MAX_FL field resets to 1518 decimal and can
be programmed either smaller or larger (up to 2k-1). The recommended default value to be
programmed by the user is 1518 or 1522 (if VLAN Tags are supported).
30
0000_0
Figure 11-18. Maximum Frame Length Register (MFLR)
—
29
Table 11-21. MFLR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
11
HASH
0000_0000_0000_0000
10
MBAR + 0x948
Read/Write
Read/Write
24
Description
23
101_1110_1110
MAX_FL
—
Freescale Semiconductor
16
0
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