MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 251
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11.5.22 Initialization Sequence
This section describes which registers and RAM locations are reset due to hardware reset, which are reset
due to the FEC reset, and what locations the user must initialize before enabling the FEC.
As soon as the FEC is initialized and enabled, it operates autonomously. Typically, the driver writes only
to RDAR, TDAR, and EIR during operation.
11.5.22.1 Hardware Initialization
In the FEC, hardware resets only those registers that generate interrupts to the MCF5272 processor or
cause conflict on bidirectional buses. The registers are reset due to a hardware reset.
Other registers reset whenever the ETHER_EN bit is cleared. Clearing ETHER_EN immediately stops all
DMA and transmit activity after a bad CRC is sent, as shown in
11.5.23 User Initialization (Prior to Asserting ETHER_EN)
The user must initialize portions the FEC prior to setting the ETHER_EN bit. The exact values depend on
the particular application. The sequence is similar to the procedure defined in
Freescale Semiconductor
System/User
User/System
Step
System
User
MCF5272 ColdFire
1
2
3
4
5
6
System
User
Table 11-32. User Initialization Process (before ETHER_EN)
Table 11-30. Hardware Initialization
Register/Machine
®
MII State Machine
XMIT block
DMA block
Table 11-31. ETHER_EN = 0
Location
Integrated Microprocessor User’s Manual, Rev. 3
RDAR
TDAR
MSCR
EIMR
ECR
EIR
Set IVSR (define ILEVEL)
Set MAUR and MALR
Set FRSR (optional)
Set TFSR (optional)
Description
Set EIMR
Clear EIR
All DMA activity is terminated
Transmission is Aborted
Prevent conflict on MMFR
Table 11-31
Reset Value
Cleared
Cleared
Effect
Cleared
Cleared
Cleared
Cleared
Table
11-32.
Ethernet Module
11-33
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