HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 126
![MCU 3/5V 60K PB-FREE 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
HD64F3437STF16V
Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of HD64F3437STF16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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External Clock Input: The external clock signal should have the same frequency as the desired
system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6.
Table 6.3
Item
Low pulse
width of external
clock input
High pulse
width of external
clock input
External clock
rise time
External clock
fall time
Clock pulse
width low
Clock pulse
width high
Table 6.4 lists the external clock output stabilization delay time. Figure 6.7 shows the timing for
the external clock output stabilization delay time. The oscillator and duty correction circuit have
the function of regulating the waveform of the external clock input to the EXTAL pin. When the
specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after
the elapse of the external clock output stabilization delay time (t
confirmed during the t
maintained during this time.
94
EXTAL
Clock Timing
Symbol
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
period, the reset signal should be driven low and the reset state
Figure 6.6 External Clock Input Timing
V
5.5 V
Min
40
40
—
—
0.3
0.4
0.3
0.4
CC
= 2.7 to
t
EXr
Max
—
—
10
10
0.7
0.6
0.7
0.6
t
EXH
V
5.5 V
Min
30
30
—
—
0.3
0.4
0.3
0.4
CC
= 4.0 to
Max
—
—
10
10
0.7
0.6
0.7
0.6
V
Min
20
20
—
—
0.3
0.4
0.3
0.4
t
EXt
10%
CC
= 5.0 V
DEXT
Max
—
—
5
5
0.7
0.6
0.7
0.6
t
EXL
). As clock signal output is not
Unit Test Conditions
ns
ns
ns
ns
t
t
t
t
cyc
cyc
cyc
cyc
Figure 6.6
ø
ø < 5 MHz 23.7
ø
ø < 5 MHz
V
5 MHz Figure
5 MHz
CC
0.5
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