HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 347
![MCU 3/5V 60K PB-FREE 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
HD64F3437STF16V
Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of HD64F3437STF16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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SDA
SCL
Internal clock
BBSY bit
Note that the clock may not be output properly during the next master send if receive data
(ICDR data) is read during the time between when the instruction to issue a stop condition is
executed (writing 0 to BBSY and SCP in ISSR) and when the stop condition is actually
generated.
In addition, overwriting of IIC control bits in order to change the send or receive operation
mode or to change settings, such as for example clearing the MST bit after completion of
master send or receive, should always be performed during the period indicated as (a) in Figure
13.21 below (after confirming that the BBSY bit in the ICCR register has been cleared to 0).
SCL
SDA
IRIC
Figure 13.21 Precautions when Reading Master Receive Data
Bit 0
Figure 13.20 IRIC Flag Clear Timing when WAIT = 1
8
Master receive mode
SCL determined to be low level
Execution of issue
stop condition instruction
(BBSY = 0 and SCP = 0 written)
A
9
SCL low level detected
VIH
SCL high level duration maintained
prohibited duration
ICDR read F
Stop condition generated
(BBSY = 0 read)
Stop condition
IRIC cleared
(a)
Start condition issued
Start condition
315
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