HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 393
HD6477021X20V
Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6477021X20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Start
Parity
Stop
Parity
Stop
Start
1
1
Data
Data
bit
bit
bit
bit
bit
bit
Serial
Idle (mark
0
D
D
D
0/1
1
0
D
D
D
0/1
0
0
1
7
0
1
7
data
state)
TDRE
FER
RXI request
RXI interrupt handler
Framing error,
1 frame
reads data in RDR
ERI request
and clears RDRF to 0
Figure 13.8 Example of SCI Receive Operation (8-bit data with parity and one stop bit)
13.3.3
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.9 shows the example of communication among processors using the multiprocessor
format.
RENESAS 376
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