MC711K4CFNE3 Freescale Semiconductor, MC711K4CFNE3 Datasheet - Page 239

• Manufacturer Part Number: MC711K4CFNE3
• Description: IC MCU 8BIT 24K EPROM 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711K4CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11K Family
MOTOROLA
1. Configuration at reset
CSPROG
CSGP1,
CSGP2
CSIO
Enable
Valid
Polarity
Size
Start address
Stretch
Enable
Valid
Polarity
Size
Start address
Stretch
Priority
Enable
Valid
Polarity
Size
Start address
Stretch
Other
Table 11-4. Chip Select Control Parameter Summary
Freescale Semiconductor, Inc.
IOEN in CSCTL
IOCSA in CSCTL
IOPL in CSCTL
IOSZ in CSCTL
Fixed (see size)
IO1S[A:B] in CSCSTR
PCSEN in CSCTL
Fixed (address valid)
Fixed (active low)
PCSZ[A:B] in CSCTL
Fixed (see size)
PCS[A:B] in CSCSTR
GCSPR in CSCTL
Set size to 0K to disable
G1AV in GPCS1C
G2AV in GPCS2C
G1POL in GPS1C
G2POL in GPS2C
G1SZ[A:D] in GPCS1C
G1SZ[A:D] in GPCS2C
GPCS1A
GPCS2A
CSCSTR
G1DG2 in GPCS1C
G1DPC in GPCS1C
G2DPC in GPCS2C
MXGS2 in MMSIZ
MXGS1 in MMSIZ
For More Information On This Product,
Memory Expansion and Chip Selects
Go to: www.freescale.com
1 = enabled, 0 = disabled
1 = address valid, 0
1 = active high, 0 = active low
1 = 4 K ($1000–$1FFF)
0 = 8 K ($0000–$1FFF)
0
1 = enabled
0:0 = 64 K ($0000–$FFFF)
0:1 = 32 K ($8000–$FFFF)
1:0 = 16 K ($C000–$FFFF)
1:1 = 8 K ($E000–$FFFF)
0
1 = CSGPx above CSPROG
0
1 = address valid, 0 = E high
1 = active high, 0 = active low
2 K to 512 K in nine steps
0K = disabled
expansion window 1 or window 2
0
Allows CSGP1 and CSGP2 to be logically ORed
and driven out the CSGP2 pin
Allows CSGP1 and CSPROG to be logically
ORed and driven out the CSPROG pin
Allows CSGP2 and CSPROG to be logically
ORed and driven out the CSPROG pin.
Allows CSGP2 to follow either 64 K CPU
addresses or 512K expansion addresses
Allows CSGP1 to follow either 64 K CPU
addresses or 512K expansion addresses
(1)
(1)
(1)
(1)
, 1, 2, or 3 E clocks
, 1, 2, or 3 E clocks
, 1, 2, or 3 E clocks
= CSPROG above CSGPx
(1)
Memory Expansion and Chip Selects
(1)
, 0 = disabled
can also follow memory
(1)
= E high
(1)
(1)
(1)
(1)
(1)
(1)
Technical Data
Chip Selects
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